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Pack P register properly

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This commit is contained in:
Eddie Hung 2019-08-01 15:10:43 -07:00
parent 105aaeaf59
commit ed7540a46f
1 changed files with 4 additions and 2 deletions
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6
passes/pmgen/xilinx_dsp.cc
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@ -86,14 +86,16 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
else else
D = st.ffP->getPort("\\D"); D = st.ffP->getPort("\\D");
SigSpec Q = st.ffP->getPort("\\Q"); SigSpec Q = st.ffP->getPort("\\Q");
P.replace(D, Q); P.replace(pm.sigmap(D), Q);
cell->setPort("\\P", Q); cell->setPort("\\P", P);
cell->setParam("\\PREG", State::S1); cell->setParam("\\PREG", State::S1);
if (st.ffP->type == "$dff") if (st.ffP->type == "$dff")
cell->setPort("\\CEP", State::S1); cell->setPort("\\CEP", State::S1);
else if (st.ffP->type == "$dffe") else if (st.ffP->type == "$dffe")
cell->setPort("\\CEP", st.ffP->getPort("\\EN")); cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
else log_abort(); else log_abort();
st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
} }
log(" clock: %s (%s)", log_signal(st.clock), "posedge"); log(" clock: %s (%s)", log_signal(st.clock), "posedge");