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https://github.com/YosysHQ/yosys
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Added "opt_rmdff -keepdc"
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parent
ca5462523e
commit
ed519f578e
2 changed files with 20 additions and 7 deletions
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@ -29,6 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
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SigMap assign_map, dff_init_map;
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SigSet<RTLIL::Cell*> mux_drivers;
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dict<SigBit, pool<SigBit>> init_attributes;
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bool keepdc;
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void remove_init_attr(SigSpec sig)
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{
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@ -115,7 +116,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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bool has_init = false;
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) {
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if (bit.wire == NULL)
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if (bit.wire == NULL || keepdc)
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has_init = true;
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val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
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}
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@ -182,7 +183,7 @@ struct OptRmdffPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_rmdff [selection]\n");
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log(" opt_rmdff [-keepdc] [selection]\n");
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log("\n");
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log("This pass identifies flip-flops with constant inputs and replaces them with\n");
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log("a constant driver.\n");
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@ -193,7 +194,17 @@ struct OptRmdffPass : public Pass {
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int total_count = 0, total_initdrv = 0;
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log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
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extra_args(args, 1, design);
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keepdc = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-keepdc") {
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keepdc = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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