From ed4b2834ef6ed811318c897bd6f8b19b6ec15f38 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 13 Aug 2019 12:19:26 -0700
Subject: [PATCH] Add assign PCOUT = P to DSP48E1
---
techlibs/xilinx/cells_sim.v | 2 ++
1 file changed, 2 insertions(+)
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 2731cb454..02ce0d61b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -784,4 +784,6 @@ module DSP48E1 (
end
endgenerate
+ assign PCOUT = P;
+
endmodule