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Merge remote-tracking branch 'origin/master' into xc7dsp

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This commit is contained in:
Eddie Hung 2019-08-01 12:02:16 -07:00
commit ed303b07b7
25 changed files with 219 additions and 86 deletions
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4
techlibs/intel/Makefile.inc
View file

@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))

0
techlibs/intel/common/brams.txt → techlibs/intel/common/brams_m9k.txt
View file

0
techlibs/intel/common/brams_map.v → techlibs/intel/common/brams_map_m9k.v
View file

28
techlibs/intel/synth_intel.cc
View file

@ -61,8 +61,8 @@ struct SynthIntelPass : public ScriptPass {
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noiopads\n");
log(" do not use IO pad cells in output netlist\n");
log(" -iopads\n");
log(" use IO pad cells in output netlist\n");
log("\n");
log(" -nobram\n");
log(" do not use block RAM cells in output netlist\n");
@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass {
}
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram, noiopads;
bool retime, flatten, nobram, iopads;
void clear_flags() YS_OVERRIDE
{
@ -90,7 +90,7 @@ struct SynthIntelPass : public ScriptPass {
retime = false;
flatten = true;
nobram = false;
noiopads = false;
iopads = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -125,8 +125,8 @@ struct SynthIntelPass : public ScriptPass {
run_to = args[argidx].substr(pos + 1);
continue;
}
if (args[argidx] == "-noiopads") {
noiopads = true;
if (args[argidx] == "-iopads") {
iopads = true;
continue;
}
if (args[argidx] == "-nobram") {
@ -187,8 +187,15 @@ struct SynthIntelPass : public ScriptPass {
}
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v");
if (family_opt == "cycloneiv" ||
family_opt == "cycloneive" ||
family_opt == "max10" ||
help_mode) {
run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
} else {
log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str());
}
}
if (check_label("map_ffram")) {
@ -215,10 +222,9 @@ struct SynthIntelPass : public ScriptPass {
}
if (check_label("map_cells")) {
if (!noiopads)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
if (iopads || help_mode)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");
}

4
techlibs/xilinx/cells_map.v
View file

@ -24,9 +24,9 @@ module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLA
(* techmap_celltype = "$_DFF_PN0_" *)
module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
(* techmap_celltype = "$_DFF_NN1_" *)
module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
(* techmap_celltype = "$_DFF_PN1_" *)
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;

6
techlibs/xilinx/xc6s_brams_map.v
View file

@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
.CLKBRDCLK(CLK2 ^ !CLKPOL2),
.ENBRDEN(A1EN),
.REGCEBREGCE(|1),
.RSTB(|0)
.RSTBRST(|0)
);
endmodule
@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1),
.REGCEBREGCE(|0),
.RSTB(|0),
.RSTBRST(|0),
.WEBWEU(B1EN_2)
);
end else begin
@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1),
.REGCEBREGCE(|0),
.RSTB(|0),
.RSTBRST(|0),
.WEBWEU(B1EN_2)
);
end endgenerate