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Standardize convention, add back test, update README

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This commit is contained in:
Akash Levy 2024-09-23 06:06:43 -07:00
parent 9e9d4359d4
commit ed2c65314b
13 changed files with 17 additions and 9 deletions
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17
tests/various/ice40_mince_abc9.ys.DISABLED Normal file
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read_verilog <<EOT
module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
reg [2:0] aa, bb;
always @(posedge clk) begin
if (ce) begin
aa <= a;
end
bb <= b;
q <= aa + bb;
end
endmodule
EOT
synth_ice40 -abc9 -dffe_min_ce_use 4