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Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT

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This commit is contained in:
Eddie Hung 2019-09-20 10:00:09 -07:00
parent 1844498c5f
commit ed187ef1cf
4 changed files with 104 additions and 53 deletions
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passes/pmgen/xilinx_dsp.pmg
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@ -1,4 +1,4 @@
pattern xilinx_dsp
pattern xilinx_dsp_pack
udata <std::function<SigSpec(const SigSpec&)>> unextend
state <SigBit> clock