mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
add pmux option to bmuxmap for better fsm detection with verific frontend
This commit is contained in:
parent
d11cb6901f
commit
ecfa7e9fbc
2 changed files with 75 additions and 6 deletions
|
@ -36,10 +36,16 @@ struct BmuxmapPass : public Pass {
|
|||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
bool pmux_mode = false;
|
||||
|
||||
log_header(design, "Executing BMUXMAP pass.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-pmux") {
|
||||
pmux_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
@ -53,18 +59,36 @@ struct BmuxmapPass : public Pass {
|
|||
SigSpec sel = cell->getPort(ID::S);
|
||||
SigSpec data = cell->getPort(ID::A);
|
||||
int width = GetSize(cell->getPort(ID::Y));
|
||||
int s_width = GetSize(cell->getPort(ID::S));
|
||||
|
||||
for (int idx = 0; idx < GetSize(sel); idx++) {
|
||||
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
|
||||
for (int i = 0; i < GetSize(new_data); i += width) {
|
||||
RTLIL::Cell *mux = module->addMux(NEW_ID,
|
||||
if(pmux_mode)
|
||||
{
|
||||
int num_cases = 1 << s_width;
|
||||
SigSpec new_a = SigSpec(State::Sx, width);
|
||||
SigSpec new_s = module->addWire(NEW_ID, num_cases);
|
||||
SigSpec new_data = module->addWire(NEW_ID, width);
|
||||
for (int val = 0; val < num_cases; val++)
|
||||
{
|
||||
module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
|
||||
}
|
||||
RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data);
|
||||
pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
|
||||
data = new_data;
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int idx = 0; idx < GetSize(sel); idx++) {
|
||||
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
|
||||
for (int i = 0; i < GetSize(new_data); i += width) {
|
||||
RTLIL::Cell *mux = module->addMux(NEW_ID,
|
||||
data.extract(i*2, width),
|
||||
data.extract(i*2+width, width),
|
||||
sel[idx],
|
||||
new_data.extract(i, width));
|
||||
mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
|
||||
mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
|
||||
}
|
||||
data = new_data;
|
||||
}
|
||||
data = new_data;
|
||||
}
|
||||
|
||||
module->connect(cell->getPort(ID::Y), data);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue