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Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md

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Eddie Hung 2019-12-30 14:24:58 -08:00
parent a038294a87
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1
CHANGELOG
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@ -57,6 +57,7 @@ Yosys 0.9 .. Yosys 0.9-dev
always_latch and always_ff) always_latch and always_ff)
- Added "xilinx_dffopt" pass - Added "xilinx_dffopt" pass
- Added "scratchpad" pass - Added "scratchpad" pass
- Added "synth_xilinx -dff"
Yosys 0.8 .. Yosys 0.9 Yosys 0.8 .. Yosys 0.9
---------------------- ----------------------

6
README.md
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@ -378,6 +378,12 @@ Verilog Attributes and non-standard features
for example, to specify the clk-to-Q delay of a flip-flop for consideration for example, to specify the clk-to-Q delay of a flip-flop for consideration
during techmapping. during techmapping.
- The module attribute ``abc9_flop`` is a boolean marking the module as a
whitebox that describes the synchronous behaviour of a flip-flop.
- The cell attribute ``abc9_keep`` is a boolean indicating that this black/
white box should be preserved through `abc9` mapping.
- The frontend sets attributes ``always_comb``, ``always_latch`` and - The frontend sets attributes ``always_comb``, ``always_latch`` and
``always_ff`` on processes derived from SystemVerilog style always blocks ``always_ff`` on processes derived from SystemVerilog style always blocks
according to the type of the always. These are checked for correctness in according to the type of the always. These are checked for correctness in