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Improved handling of reg init in opt_share and opt_rmdff

This commit is contained in:
Clifford Wolf 2014-02-04 12:02:47 +01:00
parent 9e938aa32a
commit ecdf1f5577
2 changed files with 48 additions and 7 deletions

View file

@ -35,6 +35,7 @@ struct OptShareWorker
RTLIL::Design *design;
RTLIL::Module *module;
SigMap assign_map;
SigMap dff_init_map;
CellTypes ct;
int total_count;
@ -178,6 +179,16 @@ struct OptShareWorker
return true;
}
if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections.at("\\Q")).to_sigbit_vector();
std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections.at("\\Q")).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++)
if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
lt = q1.at(i) < q2.at(i);
return true;
}
}
return false;
}
@ -189,6 +200,9 @@ struct OptShareWorker
if (!ct.cell_known(cell1->type))
return cell1 < cell2;
if (cell1->get_bool_attribute("\\keep") || cell2->get_bool_attribute("\\keep"))
return cell1 < cell2;
bool lt;
if (compare_cell_parameters_and_connections(cell1, cell2, lt))
return lt;
@ -222,6 +236,11 @@ struct OptShareWorker
log("Finding identical cells in module `%s'.\n", module->name.c_str());
assign_map.set(module);
dff_init_map.set(module);
for (auto &it : module->wires)
if (it.second->attributes.count("\\init") != 0)
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
bool did_something = true;
while (did_something)
{