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Improved handling of reg init in opt_share and opt_rmdff
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parent
9e938aa32a
commit
ecdf1f5577
2 changed files with 48 additions and 7 deletions
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@ -35,6 +35,7 @@ struct OptShareWorker
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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SigMap dff_init_map;
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CellTypes ct;
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int total_count;
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@ -178,6 +179,16 @@ struct OptShareWorker
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return true;
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}
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if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
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std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections.at("\\Q")).to_sigbit_vector();
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std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections.at("\\Q")).to_sigbit_vector();
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for (size_t i = 0; i < q1.size(); i++)
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if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
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lt = q1.at(i) < q2.at(i);
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return true;
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}
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}
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return false;
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}
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@ -189,6 +200,9 @@ struct OptShareWorker
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if (!ct.cell_known(cell1->type))
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return cell1 < cell2;
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if (cell1->get_bool_attribute("\\keep") || cell2->get_bool_attribute("\\keep"))
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return cell1 < cell2;
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bool lt;
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if (compare_cell_parameters_and_connections(cell1, cell2, lt))
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return lt;
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@ -222,6 +236,11 @@ struct OptShareWorker
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log("Finding identical cells in module `%s'.\n", module->name.c_str());
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assign_map.set(module);
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dff_init_map.set(module);
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for (auto &it : module->wires)
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if (it.second->attributes.count("\\init") != 0)
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dff_init_map.add(it.second, it.second->attributes.at("\\init"));
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bool did_something = true;
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while (did_something)
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{
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