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Added "yosys -X"

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This commit is contained in:
Clifford Wolf 2014-12-29 13:33:33 +01:00
parent 3ff0d04555
commit ecd64182c5
7 changed files with 153 additions and 1 deletions
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37
kernel/rtlil.cc
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@ -269,6 +269,11 @@ void RTLIL::Design::add(RTLIL::Module *module)
for (auto mon : monitors)
mon->notify_module_add(module);
if (yosys_xtrace) {
log("#X# New Module: %s\n", log_id(module));
log_backtrace("-X- ", yosys_xtrace-1);
}
}
RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
@ -284,6 +289,11 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
for (auto mon : monitors)
mon->notify_module_add(module);
if (yosys_xtrace) {
log("#X# New Module: %s\n", log_id(module));
log_backtrace("-X- ", yosys_xtrace-1);
}
return module;
}
@ -353,6 +363,11 @@ void RTLIL::Design::remove(RTLIL::Module *module)
for (auto mon : monitors)
mon->notify_module_del(module);
if (yosys_xtrace) {
log("#X# Remove Module: %s\n", log_id(module));
log_backtrace("-X- ", yosys_xtrace-1);
}
log_assert(modules_.at(module->name) == module);
modules_.erase(module->name);
delete module;
@ -1283,6 +1298,11 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn)
for (auto mon : design->monitors)
mon->notify_connect(this, conn);
if (yosys_xtrace) {
log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
log_backtrace("-X- ", yosys_xtrace-1);
}
connections_.push_back(conn);
}
@ -1300,6 +1320,13 @@ void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
for (auto mon : design->monitors)
mon->notify_connect(this, new_conn);
if (yosys_xtrace) {
log("#X# New connections vector in %s:\n", log_id(this));
for (auto &conn: new_conn)
log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
log_backtrace("-X- ", yosys_xtrace-1);
}
connections_ = new_conn;
}
@ -1795,6 +1822,11 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
for (auto mon : module->design->monitors)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);
if (yosys_xtrace) {
log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
log_backtrace("-X- ", yosys_xtrace-1);
}
connections_.erase(conn_it);
}
}
@ -1816,6 +1848,11 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
for (auto mon : module->design->monitors)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);
if (yosys_xtrace) {
log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
log_backtrace("-X- ", yosys_xtrace-1);
}
conn_it->second = signal;
}