From ecd289b9969bcf531ba1fcfe5f2599e848b7042a Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Mon, 17 Mar 2025 00:38:32 -0700 Subject: [PATCH] Small simplemap rename --- passes/techmap/simplemap.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 4ca3b8ab7..4e596911c 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); bool is_ne = cell->type.in(ID($ne), ID($nex)); - RTLIL::SigSpec xor_out = module->addWire(NEW_ID2_SUFFIX("xor_out"), max(GetSize(sig_a), GetSize(sig_b))); // SILIMATE: Improve the naming + RTLIL::SigSpec xor_out = module->addWire(NEW_ID2_SUFFIX("xor"), max(GetSize(sig_a), GetSize(sig_b))); // SILIMATE: Improve the naming RTLIL::Cell *xor_cell = module->addXor(NEW_ID2, sig_a, sig_b, xor_out, is_signed, cell->get_src_attribute()); // SILIMATE: Improve the naming xor_cell->attributes = cell->attributes; simplemap_bitop(module, xor_cell);