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	Add write_xaiger
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					 2 changed files with 11 additions and 21 deletions
				
			
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					@ -1,3 +1,4 @@
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OBJS += backends/aiger/aiger.o
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					OBJS += backends/aiger/aiger.o
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					OBJS += backends/aiger/xaiger.o
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					@ -35,7 +35,7 @@ void aiger_encode(std::ostream &f, int x)
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	f.put(x);
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						f.put(x);
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}
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					}
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struct AigerWriter
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					struct XAigerWriter
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{
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					{
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	Module *module;
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						Module *module;
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	bool zinit_mode;
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						bool zinit_mode;
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					@ -100,7 +100,7 @@ struct AigerWriter
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		return aig_map.at(bit);
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							return aig_map.at(bit);
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	}
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						}
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	AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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						XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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	{
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						{
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		pool<SigBit> undriven_bits;
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							pool<SigBit> undriven_bits;
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		pool<SigBit> unused_bits;
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							pool<SigBit> unused_bits;
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					@ -669,20 +669,16 @@ struct AigerWriter
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	}
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						}
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};
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					};
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struct AigerBackend : public Backend {
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					struct XAigerBackend : public Backend {
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	AigerBackend() : Backend("aiger", "write design to AIGER file") { }
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						XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
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	void help() YS_OVERRIDE
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						void help() YS_OVERRIDE
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	{
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						{
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		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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							//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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		log("\n");
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							log("\n");
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		log("    write_aiger [options] [filename]\n");
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							log("    write_xaiger [options] [filename]\n");
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		log("\n");
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							log("\n");
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		log("Write the current design to an AIGER file. The design must be flattened and\n");
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							log("Write the current design to an XAIGER file. The design must be flattened and\n");
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		log("must not contain any cell types except $_AND_, $_NOT_, simple FF types,\n");
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							log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
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		log("$assert and $assume cells, and $initstate cells.\n");
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		log("\n");
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		log("$assert and $assume cells are converted to AIGER bad state properties and\n");
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		log("invariant constraints.\n");
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		log("\n");
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							log("\n");
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		log("    -ascii\n");
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							log("    -ascii\n");
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		log("        write ASCII version of AGIER format\n");
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							log("        write ASCII version of AGIER format\n");
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					@ -691,9 +687,6 @@ struct AigerBackend : public Backend {
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		log("        convert FFs to zero-initialized FFs, adding additional inputs for\n");
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							log("        convert FFs to zero-initialized FFs, adding additional inputs for\n");
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		log("        uninitialized FFs.\n");
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							log("        uninitialized FFs.\n");
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		log("\n");
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							log("\n");
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		log("    -miter\n");
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		log("        design outputs are AIGER bad state properties\n");
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		log("\n");
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		log("    -symbols\n");
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							log("    -symbols\n");
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		log("        include a symbol table in the generated AIGER file\n");
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							log("        include a symbol table in the generated AIGER file\n");
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		log("\n");
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							log("\n");
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					@ -721,7 +714,7 @@ struct AigerBackend : public Backend {
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		bool bmode = false;
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							bool bmode = false;
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		std::string map_filename;
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							std::string map_filename;
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		log_header(design, "Executing AIGER backend.\n");
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							log_header(design, "Executing XAIGER backend.\n");
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		size_t argidx;
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							size_t argidx;
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		for (argidx = 1; argidx < args.size(); argidx++)
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							for (argidx = 1; argidx < args.size(); argidx++)
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					@ -734,10 +727,6 @@ struct AigerBackend : public Backend {
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				zinit_mode = true;
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									zinit_mode = true;
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				continue;
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									continue;
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			}
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								}
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			if (args[argidx] == "-miter") {
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				miter_mode = true;
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				continue;
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			}
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			if (args[argidx] == "-symbols") {
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								if (args[argidx] == "-symbols") {
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				symbols_mode = true;
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									symbols_mode = true;
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				continue;
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									continue;
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					@ -772,7 +761,7 @@ struct AigerBackend : public Backend {
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		if (top_module == nullptr)
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							if (top_module == nullptr)
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			log_error("Can't find top module in current design!\n");
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								log_error("Can't find top module in current design!\n");
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		AigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
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							XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
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		writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
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							writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
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		if (!map_filename.empty()) {
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							if (!map_filename.empty()) {
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					@ -783,6 +772,6 @@ struct AigerBackend : public Backend {
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			writer.write_map(mapf, verbose_map);
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								writer.write_map(mapf, verbose_map);
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		}
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							}
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	}
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						}
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} AigerBackend;
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					} XAigerBackend;
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PRIVATE_NAMESPACE_END
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					PRIVATE_NAMESPACE_END
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