mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Modify arguments to match existing style.

Browse source 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-03-01 12:14:27 -08:00
parent 3090951d54
commit eccaf101d8
2 changed files with 11 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

10
manual/command-reference-manual.tex
View file

@ -4247,10 +4247,10 @@ compatible with 7-Series Xilinx devices.
generate an output netlist (and BLIF file) suitable for VPR. generate an output netlist (and BLIF file) suitable for VPR.
(this feature is experimental and incomplete) (this feature is experimental and incomplete)
-no-brams -nobrams
disable infering of block rams disable infering of block rams
-no-drams -nodrams
disable infering of distributed rams disable infering of distributed rams
-run <from_label>:<to_label> -run <from_label>:<to_label>
@ -4280,11 +4280,11 @@ The following commands are executed by this synthesis command:
coarse: coarse:
synth -run coarse synth -run coarse
bram: (only executed when '-no-brams' is not given) bram: (only executed when '-nobrams' is not given)
memory_bram -rules +/xilinx/brams.txt memory_bram -rules +/xilinx/brams.txt
techmap -map +/xilinx/brams_map.v techmap -map +/xilinx/brams_map.v
dram: (only executed when '-no-drams' is not given) dram: (only executed when '-nodrams' is not given)
memory_bram -rules +/xilinx/drams.txt memory_bram -rules +/xilinx/drams.txt
techmap -map +/xilinx/drams_map.v techmap -map +/xilinx/drams_map.v

12
techlibs/xilinx/synth_xilinx.cc
View file

@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass
log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n"); log(" (this feature is experimental and incomplete)\n");
log("\n"); log("\n");
log(" -no-brams\n"); log(" -nobrams\n");
log(" disable infering of block rams\n"); log(" disable infering of block rams\n");
log("\n"); log("\n");
log(" -no-drams\n"); log(" -nodrams\n");
log(" disable infering of distributed rams\n"); log(" disable infering of distributed rams\n");
log("\n"); log("\n");
log(" -run <from_label>:<to_label>\n"); log(" -run <from_label>:<to_label>\n");
@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass
log(" coarse:\n"); log(" coarse:\n");
log(" synth -run coarse\n"); log(" synth -run coarse\n");
log("\n"); log("\n");
log(" bram: (only executed when '-no-brams' is not given)\n"); log(" bram: (only executed when '-nobrams' is not given)\n");
log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" memory_bram -rules +/xilinx/brams.txt\n");
log(" techmap -map +/xilinx/brams_map.v\n"); log(" techmap -map +/xilinx/brams_map.v\n");
log("\n"); log("\n");
log(" dram: (only executed when '-no-drams' is not given)\n"); log(" dram: (only executed when '-nodrams' is not given)\n");
log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" memory_bram -rules +/xilinx/drams.txt\n");
log(" techmap -map +/xilinx/drams_map.v\n"); log(" techmap -map +/xilinx/drams_map.v\n");
log("\n"); log("\n");
@ -182,11 +182,11 @@ struct SynthXilinxPass : public Pass
vpr = true; vpr = true;
continue; continue;
} }
if (args[argidx] == "-no-brams") { if (args[argidx] == "-nobrams") {
noBrams = true; noBrams = true;
continue; continue;
} }
if (args[argidx] == "-no-drams") { if (args[argidx] == "-nodrams") {
noDrams = true; noDrams = true;
continue; continue;
} }