diff --git a/tests/various/muxpack_wide_y.ys b/tests/various/muxpack_wide_y.ys
new file mode 100644
index 000000000..142119875
--- /dev/null
+++ b/tests/various/muxpack_wide_y.ys
@@ -0,0 +1,9 @@
+# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
+# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
+read_verilog <<EOT
+module top(input b, output [18:0] h);
+  assign h = ~|b;
+endmodule
+EOT
+proc
+muxpack