mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-07 06:33:24 +00:00
Code Activity

Add some debug to abc9

Browse source
This commit is contained in:
Eddie Hung 2019-05-29 15:21:41 -07:00
parent 92197326b8
commit ecaa7856e9
1 changed files with 19 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

20
passes/techmap/abc9.cc
View file

@ -423,6 +423,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
#if 0
std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
log_assert(!design->module("$__abc9__"));
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
reader.parse_xaiger();
ifs.close();
Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v"));
design->remove(design->module("$__abc9__"));
#endif
design->selection_stack.pop_back(); design->selection_stack.pop_back();
// Now 'unexpose' those wires by undoing // Now 'unexpose' those wires by undoing
@ -540,9 +555,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
log_assert(!design->module("$__abc9__")); log_assert(!design->module("$__abc9__"));
AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
reader.parse_xaiger(); reader.parse_xaiger();
ifs.close(); ifs.close();
#if 0
Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v"));
#endif
log_header(design, "Re-integrating ABC9 results.\n"); log_header(design, "Re-integrating ABC9 results.\n");
RTLIL::Module *mapped_mod = design->module("$__abc9__"); RTLIL::Module *mapped_mod = design->module("$__abc9__");
if (mapped_mod == NULL) if (mapped_mod == NULL)