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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:48:26 +02:00
parent a8d3a68971
commit ec923652e2
16 changed files with 43 additions and 51 deletions
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2
passes/techmap/extract.cc
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@ -315,7 +315,7 @@ namespace
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
}
}