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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:48:26 +02:00
parent a8d3a68971
commit ec923652e2
16 changed files with 43 additions and 51 deletions
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4
passes/sat/eval.cc
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@ -260,8 +260,8 @@ struct VlogHammerReporter
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wires.at(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec::grml(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j));
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits.push_back(bits.back());
bits.pop_back();
}