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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
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16 changed files with 43 additions and 51 deletions
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@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
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for (auto &it : module->wires) {
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RTLIL::Wire *wire = it.second;
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for (int i = 0; i < wire->width; i++) {
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RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1);
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RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1);
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if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
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assign_map.add(s1);
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}
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