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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:48:26 +02:00
parent a8d3a68971
commit ec923652e2
16 changed files with 43 additions and 51 deletions
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2
passes/abc/abc.cc
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@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
clk_str = clk_str.substr(1);
}
if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0));
clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0));
}
if (dff_mode && clk_sig.size() == 0)