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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:48:26 +02:00
parent a8d3a68971
commit ec923652e2
16 changed files with 43 additions and 51 deletions
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4
kernel/sigtools.h
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@ -144,7 +144,7 @@ struct SigPool
{
RTLIL::SigSpec sig;
for (auto &bit : bits) {
sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
sig.append(RTLIL::SigSpec(bit.first, bit.second));
break;
}
return sig;
@ -154,7 +154,7 @@ struct SigPool
{
RTLIL::SigSpec sig;
for (auto &bit : bits)
sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
sig.append(RTLIL::SigSpec(bit.first, bit.second));
sig.sort_and_unify();
return sig;
}