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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:48:26 +02:00
parent a8d3a68971
commit ec923652e2
16 changed files with 43 additions and 51 deletions
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4
backends/blif/blif.cc
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@ -118,7 +118,7 @@ struct BlifDumper
for (auto &it : inputs) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i)));
}
fprintf(f, "\n");
@ -126,7 +126,7 @@ struct BlifDumper
for (auto &it : outputs) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i)));
}
fprintf(f, "\n");