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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-11-05 15:40:09 -05:00 • committed by GitHub
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12
tests/various/timeest.ys Normal file
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read_verilog <<EOF
module top(input [3:0] a, input [3:0] b, output [7:0] y);
assign y = a * b;
endmodule
module top2(input [7:0] a, input [7:0] b, output [15:0] y);
assign y = a * b;
endmodule
EOF
synth
timeest