mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
Add "read_verilog -pwires" feature, closes #1106
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
5a1f1caa44
commit
ec4565009a
6 changed files with 48 additions and 9 deletions
|
@ -168,6 +168,9 @@ struct VerilogFrontend : public Frontend {
|
|||
log(" -icells\n");
|
||||
log(" interpret cell types starting with '$' as internal cell types\n");
|
||||
log("\n");
|
||||
log(" -pwires\n");
|
||||
log(" add a wire for each module parameter\n");
|
||||
log("\n");
|
||||
log(" -nooverwrite\n");
|
||||
log(" ignore re-definitions of modules. (the default behavior is to\n");
|
||||
log(" create an error message if the existing module is not a black box\n");
|
||||
|
@ -228,6 +231,7 @@ struct VerilogFrontend : public Frontend {
|
|||
bool flag_nodpi = false;
|
||||
bool flag_noopt = false;
|
||||
bool flag_icells = false;
|
||||
bool flag_pwires = false;
|
||||
bool flag_nooverwrite = false;
|
||||
bool flag_overwrite = false;
|
||||
bool flag_defer = false;
|
||||
|
@ -368,6 +372,10 @@ struct VerilogFrontend : public Frontend {
|
|||
flag_icells = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-pwires") {
|
||||
flag_pwires = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-ignore_redef" || arg == "-nooverwrite") {
|
||||
flag_nooverwrite = true;
|
||||
flag_overwrite = false;
|
||||
|
@ -458,7 +466,7 @@ struct VerilogFrontend : public Frontend {
|
|||
error_on_dpi_function(current_ast);
|
||||
|
||||
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
|
||||
flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
|
||||
flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
|
||||
|
||||
if (!flag_nopp)
|
||||
delete lexin;
|
||||
|
|
|
@ -319,15 +319,17 @@ module_para_list:
|
|||
|
||||
single_module_para:
|
||||
/* empty */ |
|
||||
TOK_PARAMETER {
|
||||
attr TOK_PARAMETER {
|
||||
if (astbuf1) delete astbuf1;
|
||||
astbuf1 = new AstNode(AST_PARAMETER);
|
||||
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
|
||||
append_attr(astbuf1, $1);
|
||||
} param_signed param_integer param_range single_param_decl |
|
||||
TOK_LOCALPARAM {
|
||||
attr TOK_LOCALPARAM {
|
||||
if (astbuf1) delete astbuf1;
|
||||
astbuf1 = new AstNode(AST_LOCALPARAM);
|
||||
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
|
||||
append_attr(astbuf1, $1);
|
||||
} param_signed param_integer param_range single_param_decl |
|
||||
single_param_decl;
|
||||
|
||||
|
@ -1217,6 +1219,7 @@ param_decl:
|
|||
attr TOK_PARAMETER {
|
||||
astbuf1 = new AstNode(AST_PARAMETER);
|
||||
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
|
||||
append_attr(astbuf1, $1);
|
||||
} param_signed param_integer param_real param_range param_decl_list ';' {
|
||||
delete astbuf1;
|
||||
};
|
||||
|
@ -1225,6 +1228,7 @@ localparam_decl:
|
|||
attr TOK_LOCALPARAM {
|
||||
astbuf1 = new AstNode(AST_LOCALPARAM);
|
||||
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
|
||||
append_attr(astbuf1, $1);
|
||||
} param_signed param_integer param_real param_range param_decl_list ';' {
|
||||
delete astbuf1;
|
||||
};
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue