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Merge 51a377be44 into 9d0cdb8551

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Zachary Snow 2026-05-23 11:42:48 +08:00 • committed by GitHub
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16
tests/simple/memwr_port_connection.sv
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@ -5,9 +5,17 @@ module producer(
endmodule
module top(
output logic [3:0] out
output logic [3:0] out0, out1, out2, out3
);
logic [3:0] v[0:0];
producer p(v[0]);
assign out = v[0];
logic [3:0] v[1:0];
logic [1:0] u[1:0];
logic [1:0] t[1:0];
producer p0(v[0]);
producer p1({v[1]});
producer p2({u[1], u[0]});
producer p3({{t[1]}, {t[0]}});
assign out0 = v[0];
assign out1 = v[1];
assign out2 = {u[1], u[0]};
assign out3 = {t[1], t[0]};
endmodule