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Towards Xilinx bram support

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This commit is contained in:
Clifford Wolf 2015-01-06 23:21:52 +01:00
parent 7cc5192125
commit ec2eef89fa
3 changed files with 65 additions and 24 deletions
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techlibs/xilinx/brams.v
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@ -167,10 +167,10 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
input CLK2;
input CLK3;
input [8:0] A1ADDR;
input [9:0] A1ADDR;
output [17:0] A1DATA;
input [8:0] B1ADDR;
input [9:0] B1ADDR;
input [17:0] B1DATA;
input [1:0] B1EN;