mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

Add $aldff and $aldffe: flip-flops with async load.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-10-01 04:33:00 +02:00
parent fbd70f28f0
commit ec2b5548fe
9 changed files with 527 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

49
techlibs/common/simlib.v
View file

@ -1890,6 +1890,30 @@ endmodule
// --------------------------------------------------------
module \$aldff (CLK, ALOAD, AD, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter ALOAD_POLARITY = 1'b1;
input CLK, ALOAD;
input [WIDTH-1:0] AD;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_aload = ALOAD == ALOAD_POLARITY;
always @(posedge pos_clk, posedge pos_aload) begin
if (pos_aload)
Q <= AD;
else
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$sdff (CLK, SRST, D, Q);
parameter WIDTH = 0;
@ -1939,6 +1963,31 @@ endmodule
// --------------------------------------------------------
module \$aldffe (CLK, ALOAD, AD, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter ALOAD_POLARITY = 1'b1;
input CLK, ALOAD, EN;
input [WIDTH-1:0] D;
input [WIDTH-1:0] AD;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_aload = ALOAD == ALOAD_POLARITY;
always @(posedge pos_clk, posedge pos_aload) begin
if (pos_aload)
Q <= AD;
else if (EN == EN_POLARITY)
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$sdffe (CLK, SRST, EN, D, Q);
parameter WIDTH = 0;