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Add $aldff and $aldffe: flip-flops with async load.

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Marcelina Kościelnicka 2021-10-01 04:33:00 +02:00
parent fbd70f28f0
commit ec2b5548fe
9 changed files with 527 additions and 2 deletions
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284
techlibs/common/simcells.v
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@ -1252,6 +1252,290 @@ always @(posedge C or posedge R) begin
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_NN_ (D, C, L, AD, Q)
//-
//- A negative edge D-type flip-flop with negative polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 0 a | a
//- d \ - - | d
//- - - - - | q
//-
module \$_ALDFF_NN_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(negedge C or negedge L) begin
if (L == 0)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_NP_ (D, C, L, AD, Q)
//-
//- A negative edge D-type flip-flop with positive polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 1 a | a
//- d \ - - | d
//- - - - - | q
//-
module \$_ALDFF_NP_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_PN_ (D, C, L, AD, Q)
//-
//- A positive edge D-type flip-flop with negative polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 0 a | a
//- d / - - | d
//- - - - - | q
//-
module \$_ALDFF_PN_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(posedge C or negedge L) begin
if (L == 0)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_PP_ (D, C, L, AD, Q)
//-
//- A positive edge D-type flip-flop with positive polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 1 a | a
//- d / - - | d
//- - - - - | q
//-
module \$_ALDFF_PP_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(posedge C or posedge L) begin
if (L == 1)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NNN_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d \ - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_NNN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NNP_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d \ - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_NNP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NPN_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d \ - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_NPN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NPP_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d \ - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_NPP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PNN_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d / - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_PNN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PNP_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d / - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_PNP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PPN_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d / - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_PPN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PPP_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d / - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_PPP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_NNN_ (C, S, R, D, Q)