diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 7e3f87147..167997dc0 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -598,6 +598,8 @@ struct RenamePass : public Pass {
 
 				for (auto &it : new_cell_names)
 					module->rename(it.first, it.second);
+
+				module->fixup_ports();
 			}
 		}
 		else
diff --git a/tests/various/rename_unescape.ys b/tests/various/rename_unescape.ys
index 546d97357..2bb5286cc 100644
--- a/tests/various/rename_unescape.ys
+++ b/tests/various/rename_unescape.ys
@@ -39,3 +39,18 @@ select -assert-count 1 w:d__1
 select -assert-count 1 w:_e
 select -assert-count 1 w:wire_
 select -assert-count 1 w:$add$<<EOF:*$1_Y
+
+# Ports are updated during rename
+design -reset
+read_verilog << EOT
+module top(output \$e );
+submod \a$ (\$e );
+endmodule
+
+module submod(output \a[0] );
+    assign \a[0] = 0;
+endmodule
+EOT
+
+rename -unescape
+check