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https://github.com/YosysHQ/yosys
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Merge pull request #5832 from YosysHQ/emil/simple-extract
rtlil: rewrite SigSpec::extract for perf and packing
This commit is contained in:
Emil J
GitHub
commit
ec0a102302
5 changed files with 198 additions and 30 deletions
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@ -5272,26 +5272,32 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
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log_assert(length >= 0);
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log_assert(offset + length <= size());
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SigSpec extracted;
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Chunks cs = chunks();
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auto it = cs.begin();
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for (; offset; offset -= it->width, ++it) {
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if (offset < it->width) {
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int chunk_length = min(it->width - offset, length);
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extracted.append(it->extract(offset, chunk_length));
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length -= chunk_length;
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++it;
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break;
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}
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}
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for (; length; length -= it->width, ++it) {
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if (length >= it->width) {
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extracted.append(*it);
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std::vector<SigBit> extracted;
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SigBit first;
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bool is_packing = true;
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for (int i = offset; i < offset + length; i++) {
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bool was_packing_before = is_packing;
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SigBit bit = (*this)[i];
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if (i == offset) {
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first = bit;
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if (!bit.wire)
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is_packing = false;
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} else {
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extracted.append(it->extract(0, length));
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break;
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if (bit.wire != first.wire)
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is_packing = false;
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if (bit.wire)
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if (bit.offset != first.offset + (i - offset))
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is_packing = false;
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}
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if (was_packing_before && !is_packing)
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for (int j = offset; j < i; j++)
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extracted.push_back((*this)[j]);
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if (!is_packing)
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extracted.push_back((*this)[i]);
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}
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if (is_packing)
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return SigChunk(first.wire, first.offset, length);
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return extracted;
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}
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@ -1400,6 +1400,8 @@ struct RTLIL::SigSpecConstIterator
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struct RTLIL::SigSpec
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{
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private:
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friend class SigSpecRepTest;
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FRIEND_TEST(SigSpecRepTest, Extract);
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enum Representation : char {
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CHUNK,
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BITS,
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71
tests/unit/kernel/rtlilHelpers.h
Normal file
71
tests/unit/kernel/rtlilHelpers.h
Normal file
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@ -0,0 +1,71 @@
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#ifndef RTLIL_HELPERS_H
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#define RTLIL_HELPERS_H
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#include <gtest/gtest.h>
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#include "kernel/rtlil.h"
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YOSYS_NAMESPACE_BEGIN
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class SigSpecRepTest : public ::testing::Test {
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protected:
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Design* d;
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Module* m;
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void SetUp() override {
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d = new Design;
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m = d->addModule("$test");
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}
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void TearDown() override {
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delete d;
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}
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// Create n wires with given width
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std::vector<Wire*> createWires(int count, int width = 4) {
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std::vector<Wire*> wires;
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for (int i = 0; i < count; i++) {
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Wire* w = m->addWire(stringf("$w%d", i), width);
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wires.push_back(w);
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}
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return wires;
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}
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// Append all wires to a SigSpec
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SigSpec wiresAsSigSpec(const std::vector<Wire*>& wires) {
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SigSpec sig;
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for (auto w : wires)
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sig.append(w);
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return sig;
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}
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// Create a SigSpec of constants
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SigSpec constsAsSigSpec(int count, int width = 4) {
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SigSpec sig;
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for (int i = 0; i < count; i++)
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sig.append(Const(i, width));
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return sig;
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}
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// Convert wires to pool of SigBits
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pool<SigBit> wiresToPool(const std::vector<Wire*>& wires) {
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pool<SigBit> pool;
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for (auto w : wires)
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for (auto &bit : SigSpec(w))
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pool.insert(bit);
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return pool;
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}
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// Convert wires to set of SigBits
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std::set<SigBit> wiresToSet(const std::vector<Wire*>& wires) {
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std::set<SigBit> set;
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for (auto w : wires)
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for (auto &bit : SigSpec(w))
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set.insert(bit);
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return set;
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}
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};
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YOSYS_NAMESPACE_END
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#endif /* RTLIL_HELPERS_H */
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89
tests/unit/kernel/sigspecExtractTest.cc
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89
tests/unit/kernel/sigspecExtractTest.cc
Normal file
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@ -0,0 +1,89 @@
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#include <gtest/gtest.h>
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#include "kernel/rtlil.h"
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#include "tests/unit/kernel/rtlilHelpers.h"
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YOSYS_NAMESPACE_BEGIN
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namespace RTLIL {
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TEST_F(SigSpecRepTest, Extract)
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{
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{
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std::vector<Wire*> wires;
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SigSpec sig;
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for (int i = 0; i < 4; i++)
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wires.push_back(m->addWire(stringf("$w%d", i), 4));
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for (auto w : wires)
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sig.append(w);
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SigSpec extractedFirst = sig.extract(0, 4);
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SigSpec extractedSecond = sig.extract(4, 4);
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SigSpec extractedLast = sig.extract(12, 4);
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EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedFirst.as_wire(), wires[0]);
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EXPECT_EQ(extractedSecond.as_wire(), wires[1]);
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EXPECT_EQ(extractedLast.as_wire(), wires[3]);
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}
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{
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std::vector<SigSpec> consts;
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SigSpec sig;
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for (int i = 0; i < 4; i++)
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consts.push_back(Const(i, 4));
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for (auto c : consts)
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sig.append(c);
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SigSpec extractedFirst = sig.extract(0, 4);
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SigSpec extractedSecond = sig.extract(4, 4);
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SigSpec extractedLast = sig.extract(12, 4);
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EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedFirst, consts[0]);
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EXPECT_EQ(extractedSecond, consts[1]);
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EXPECT_EQ(extractedLast, consts[3]);
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}
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{
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SigSpec sig;
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sig.append(Const(0, 4));
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Wire* w = m->addWire("$foo", 4);
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sig.append(w);
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sig.append(Const(15, 4));
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SigSpec extractedFirst = sig.extract(0, 4);
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SigSpec extractedSecond = sig.extract(4, 4);
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SigSpec extractedLast = sig.extract(8, 4);
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EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
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EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
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SigSpec extractedFirstTwo = sig.extract(0, 8);
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EXPECT_EQ(extractedFirstTwo.rep_, SigSpec::Representation::BITS);
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SigSpec extractedLastTwo = sig.extract(4, 8);
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EXPECT_EQ(extractedLastTwo.rep_, SigSpec::Representation::BITS);
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EXPECT_EQ(extractedFirstTwo[0], State::S0);
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EXPECT_EQ(extractedFirstTwo[1], State::S0);
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EXPECT_EQ(extractedFirstTwo[2], State::S0);
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EXPECT_EQ(extractedFirstTwo[3], State::S0);
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EXPECT_EQ(extractedFirstTwo[4], SigBit(w, 0));
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EXPECT_EQ(extractedFirstTwo[5], SigBit(w, 1));
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EXPECT_EQ(extractedFirstTwo[6], SigBit(w, 2));
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EXPECT_EQ(extractedFirstTwo[7], SigBit(w, 3));
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EXPECT_EQ(extractedLastTwo[0], SigBit(w, 0));
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EXPECT_EQ(extractedLastTwo[1], SigBit(w, 1));
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EXPECT_EQ(extractedLastTwo[2], SigBit(w, 2));
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EXPECT_EQ(extractedLastTwo[3], SigBit(w, 3));
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EXPECT_EQ(extractedLastTwo[4], State::S1);
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EXPECT_EQ(extractedLastTwo[5], State::S1);
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EXPECT_EQ(extractedLastTwo[6], State::S1);
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EXPECT_EQ(extractedLastTwo[7], State::S1);
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}
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}
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};
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YOSYS_NAMESPACE_END
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@ -5,7 +5,7 @@
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YOSYS_NAMESPACE_BEGIN
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// Test fixture with helper functions
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class SigSpecRemove2Test : public ::testing::Test {
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class SigSpecRepTest : public ::testing::Test {
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protected:
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Design* d;
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Module* m;
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@ -64,7 +64,7 @@ protected:
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}
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};
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TEST_F(SigSpecRemove2Test, WithSigSpecPattern)
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TEST_F(SigSpecRepTest, WithSigSpecPattern)
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{
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auto wires = createWires(4);
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SigSpec sig = wiresAsSigSpec(wires);
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@ -84,7 +84,7 @@ TEST_F(SigSpecRemove2Test, WithSigSpecPattern)
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, WithPoolPattern)
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TEST_F(SigSpecRepTest, WithPoolPattern)
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{
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auto wires = createWires(3);
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SigSpec sig = wiresAsSigSpec(wires);
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@ -103,7 +103,7 @@ TEST_F(SigSpecRemove2Test, WithPoolPattern)
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, WithSetPattern)
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TEST_F(SigSpecRepTest, WithSetPattern)
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{
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auto wires = createWires(3);
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SigSpec sig = wiresAsSigSpec(wires);
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@ -122,7 +122,7 @@ TEST_F(SigSpecRemove2Test, WithSetPattern)
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, ManyElements)
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TEST_F(SigSpecRepTest, ManyElements)
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{
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const int num_wires = 100;
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auto wires = createWires(num_wires);
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@ -146,7 +146,7 @@ TEST_F(SigSpecRemove2Test, ManyElements)
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}
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// Test remove2 with very large dataset to check scaling
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TEST_F(SigSpecRemove2Test, VeryLargeScalingTest)
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TEST_F(SigSpecRepTest, VeryLargeScalingTest)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires);
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@ -173,7 +173,7 @@ TEST_F(SigSpecRemove2Test, VeryLargeScalingTest)
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}
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// Test multiple sequential removals (simulates removeSignalFromCaseTree)
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TEST_F(SigSpecRemove2Test, MultipleSequentialRemovals)
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TEST_F(SigSpecRepTest, MultipleSequentialRemovals)
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{
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const int num_wires = 512;
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auto wires = createWires(num_wires);
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@ -204,7 +204,7 @@ TEST_F(SigSpecRemove2Test, MultipleSequentialRemovals)
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}
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// Test remove2 with very large dataset to check scaling
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TEST_F(SigSpecRemove2Test, PoolOverloadLargeDataset)
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TEST_F(SigSpecRepTest, PoolOverloadLargeDataset)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires, 1);
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@ -228,7 +228,7 @@ TEST_F(SigSpecRemove2Test, PoolOverloadLargeDataset)
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}
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// Test set overload (same perf characteristics as pool)
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TEST_F(SigSpecRemove2Test, SetOverloadLargeDataset)
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TEST_F(SigSpecRepTest, SetOverloadLargeDataset)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires, 1);
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@ -252,7 +252,7 @@ TEST_F(SigSpecRemove2Test, SetOverloadLargeDataset)
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}
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// Worst case: remove almost all elements
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TEST_F(SigSpecRemove2Test, RemoveAlmostAllElements)
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TEST_F(SigSpecRepTest, RemoveAlmostAllElements)
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{
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const int num_wires = 10000;
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auto wires = createWires(num_wires, 1);
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@ -269,7 +269,7 @@ TEST_F(SigSpecRemove2Test, RemoveAlmostAllElements)
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EXPECT_EQ(sig[0].wire, wires[num_wires - 1]);
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}
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TEST_F(SigSpecRemove2Test, EmptyPattern)
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TEST_F(SigSpecRepTest, EmptyPattern)
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{
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auto wires = createWires(1);
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SigSpec sig(wires[0]);
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@ -285,7 +285,7 @@ TEST_F(SigSpecRemove2Test, EmptyPattern)
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}
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// Test that NULL wire bits (constants) are not removed
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TEST_F(SigSpecRemove2Test, NullWireBitsStay)
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TEST_F(SigSpecRepTest, NullWireBitsStay)
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{
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auto wires = createWires(1);
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SigSpec sig;
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@ -309,7 +309,7 @@ TEST_F(SigSpecRemove2Test, NullWireBitsStay)
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, PartialBitRemoval)
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TEST_F(SigSpecRepTest, PartialBitRemoval)
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{
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Wire* w = m->addWire("$w1", 8);
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SigSpec sig(w);
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