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Merge pull request #5774 from Silimate/atondapu/sim-cache-sigmap

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sim: cache sigmap in register_output_step_values
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Miodrag Milanović 2026-03-25 06:40:01 +00:00 • committed by GitHub
commit ebfe5b2c06
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1 changed files with 24 additions and 14 deletions
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38
passes/sat/sim.cc
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@ -216,7 +216,13 @@ struct SimInstance
std::vector<Mem> memories; std::vector<Mem> memories;
dict<Wire*, pair<int, Const>> signal_database; struct signal_entry_t {
int id;
Const last_value;
SigSpec mapped_sig;
};
dict<Wire*, signal_entry_t> signal_database;
dict<IdString, std::map<int, pair<int, Const>>> trace_mem_database; dict<IdString, std::map<int, pair<int, Const>>> trace_mem_database;
dict<std::pair<IdString, int>, Const> trace_mem_init_database; dict<std::pair<IdString, int>, Const> trace_mem_init_database;
dict<Wire*, fstHandle> fst_handles; dict<Wire*, fstHandle> fst_handles;
@ -413,11 +419,11 @@ struct SimInstance
return result; return result;
} }
Const get_state(SigSpec sig) Const get_state_mapped(const SigSpec &mapped_sig)
{ {
Const::Builder builder(GetSize(sig)); Const::Builder builder(GetSize(mapped_sig));
for (auto bit : sigmap(sig)) for (auto bit : mapped_sig)
if (bit.wire == nullptr) if (bit.wire == nullptr)
builder.push_back(bit.data); builder.push_back(bit.data);
else if (state_nets.count(bit)) else if (state_nets.count(bit))
@ -425,7 +431,12 @@ struct SimInstance
else else
builder.push_back(State::Sz); builder.push_back(State::Sz);
Const value = builder.build(); return builder.build();
}
Const get_state(SigSpec sig)
{
Const value = get_state_mapped(sigmap(sig));
if (shared->debug) if (shared->debug)
log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value)); log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value));
return value; return value;
@ -991,7 +1002,7 @@ struct SimInstance
if (shared->hide_internal && wire->name[0] == '$') if (shared->hide_internal && wire->name[0] == '$')
continue; continue;
signal_database[wire] = make_pair(id, Const()); signal_database[wire] = {id, Const(), sigmap(wire)};
id++; id++;
} }
@ -1032,11 +1043,11 @@ struct SimInstance
hdlname.pop_back(); hdlname.pop_back();
for (auto name : hdlname) for (auto name : hdlname)
enter_scope("\\" + name); enter_scope("\\" + name);
register_signal(signal_name.c_str(), GetSize(signal.first), signal.first, signal.second.first, registers.count(signal.first)!=0); register_signal(signal_name.c_str(), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
for (auto name : hdlname) for (auto name : hdlname)
exit_scope(); exit_scope();
} else } else
register_signal(log_id(signal.first->name), GetSize(signal.first), signal.first, signal.second.first, registers.count(signal.first)!=0); register_signal(log_id(signal.first->name), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
} }
for (auto &trace_mem : trace_mem_database) for (auto &trace_mem : trace_mem_database)
@ -1108,15 +1119,14 @@ struct SimInstance
{ {
for (auto &it : signal_database) for (auto &it : signal_database)
{ {
Wire *wire = it.first; signal_entry_t &entry = it.second;
Const value = get_state(wire); Const value = get_state_mapped(entry.mapped_sig);
int id = it.second.first;
if (it.second.second == value) if (entry.last_value == value)
continue; continue;
it.second.second = value; entry.last_value = value;
data->emplace(id, value); data->emplace(entry.id, value);
} }
for (auto &trace_mem : trace_mem_database) for (auto &trace_mem : trace_mem_database)