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sv: More tests for wildcard port connections

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-11-22 12:57:51 +00:00
parent 7e741714df
commit ebe1d7d5ab
1 changed files with 57 additions and 0 deletions
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57
tests/various/sv_implicit_ports.sh
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@ -65,3 +65,60 @@ module top(input [7:0] a, output [7:0] q);
add add_i(.*); add add_i(.*);
endmodule endmodule
EOT EOT
# Parameterised module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add #(.N(8)) add_i(.*);
endmodule
EOT
# Parameterised blackbox module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
module top(input [7:0] a, b, output [7:0] q);
add #(.N(8)) add_i(.*);
endmodule
EOT
# Parameterised blackbox module - incorrect width
((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
module top(input [7:0] a, b, output [7:0] q);
add #(.N(6)) add_i(.*);
endmodule
EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
# Mixed implicit and explicit 1
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add add_i(.b(8'd42), .*);
endmodule
EOT
# Mixed implicit and explicit 2
(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, input [9:0] b, output [7:0] q);
add add_i(.b, .*);
endmodule
EOT
) 2>&1 | grep -F "Warning: Resizing cell port top.add_i.b from 10 bits to 8 bits." > /dev/null