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https://github.com/YosysHQ/yosys
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abstract: -value MVP, use buffer-normalized mode
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commit
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2 changed files with 121 additions and 62 deletions
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@ -1,9 +1,9 @@
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read_verilog <<EOT
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module half_clock (CLK, Q);
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module half_clock (CLK, Q, magic);
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input CLK;
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output reg Q;
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reg magic;
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input magic;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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@ -12,16 +12,16 @@ EOT
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proc
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# show -prefix before_base
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abstract -state -enablen magic
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check
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check -assert
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# show -prefix after_base
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design -reset
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read_verilog <<EOT
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module half_clock_en (CLK, E, Q);
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module half_clock_en (CLK, E, Q, magic);
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input CLK;
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input E;
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output reg Q;
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reg magic;
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input magic;
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always @(posedge CLK)
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if (E)
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Q <= ~Q;
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@ -33,7 +33,7 @@ opt_expr
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opt_dff
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# show -prefix before_en
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abstract -state -enablen magic
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check
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check -assert
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# show -prefix after_en
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design -reset
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@ -50,9 +50,35 @@ proc
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opt_expr
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opt_dff
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dump
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select -none
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abstract -init
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check
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select -clear
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check -assert
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# dump
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design -reset
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read_verilog <<EOT
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module main (input [3:0] baz);
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reg foo;
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reg bar;
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assign foo = bar;
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assign bar = baz[0];
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reg aaa = 1'b1;
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always @(posedge bar)
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aaa <= ~aaa;
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endmodule
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EOT
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proc -noopt
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# show -prefix before_init
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dump
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select -none
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abstract -init
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select -clear
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# show -prefix after_init
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dump
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check -assert
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# dump
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design -reset
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@ -85,6 +111,38 @@ opt_expr
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opt_dff
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# show -prefix before_a
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abstract -state -enablen magic
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check
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check -assert
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# show -prefix after_a
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# opt_clean
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# opt_clean
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design -reset
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read_verilog <<EOT
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module this_adff (CLK, ARST, D, Q, magic);
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parameter WIDTH = 2;
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parameter CLK_POLARITY = 1'b1;
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parameter ARST_POLARITY = 1'b1;
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parameter ARST_VALUE = 0;
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input CLK, ARST, magic;
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input [WIDTH-1:0] D;
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output reg [WIDTH-1:0] Q;
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wire pos_clk = CLK == CLK_POLARITY;
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wire pos_arst = ARST == ARST_POLARITY;
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always @(posedge pos_clk, posedge pos_arst) begin
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if (pos_arst)
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Q <= ARST_VALUE;
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else
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Q <= D;
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end
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endmodule
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EOT
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proc
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# show -prefix before_value
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abstract -value -enablen magic
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check -assert
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clean
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# show -prefix after_value
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# dump
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