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timinginfo: special-case $specify2 in signorm invariant
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5bfb631085
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2 changed files with 4 additions and 5 deletions
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@ -1058,7 +1058,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
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void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
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void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
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{
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{
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bool is_input_port = false;
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bool is_input_port = false;
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if (module->sig_norm_index != nullptr) {
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if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) {
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module->sig_norm_index->sigmap.apply(signal);
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module->sig_norm_index->sigmap.apply(signal);
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auto dir = port_dir(portname);
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auto dir = port_dir(portname);
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@ -106,10 +106,9 @@ struct TimingInfo
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for (const auto &c : src.chunks())
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for (const auto &c : src.chunks())
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if (!c.wire || !c.wire->port_input)
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if (!c.wire || !c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
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// TODO disabled check because signorm breaks this assumption
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for (const auto &c : dst.chunks())
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// for (const auto &c : dst.chunks())
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if (!c.wire || !c.wire->port_output)
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// if (!c.wire || !c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
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// log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
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int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
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int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
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int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
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int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
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int max = std::max(rise_max,fall_max);
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int max = std::max(rise_max,fall_max);
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