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timinginfo: special-case $specify2 in signorm invariant

This commit is contained in:
Emil J. Tywoniak 2026-03-26 19:42:33 +01:00
parent 5bfb631085
commit eb6dd47bd6
2 changed files with 4 additions and 5 deletions

View file

@ -1058,7 +1058,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
{ {
bool is_input_port = false; bool is_input_port = false;
if (module->sig_norm_index != nullptr) { if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) {
module->sig_norm_index->sigmap.apply(signal); module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname); auto dir = port_dir(portname);

View file

@ -106,10 +106,9 @@ struct TimingInfo
for (const auto &c : src.chunks()) for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input) if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src)); log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
// TODO disabled check because signorm breaks this assumption for (const auto &c : dst.chunks())
// for (const auto &c : dst.chunks()) if (!c.wire || !c.wire->port_output)
// if (!c.wire || !c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
// log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max); int max = std::max(rise_max,fall_max);