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Add $allconst and $allseq cell types

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-02-23 13:14:47 +01:00
parent 2521ed305e
commit eb67a7532b
11 changed files with 67 additions and 9 deletions
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2
kernel/celltypes.h
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@ -122,6 +122,8 @@ struct CellTypes
setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$equiv", {A, B}, {Y}, true);
}

22
kernel/rtlil.cc
View file

@ -1101,7 +1101,7 @@ namespace {
return;
}
if (cell->type.in("$anyconst", "$anyseq")) {
if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
port("\\Y", param("\\WIDTH"));
check_expected();
return;
@ -2145,6 +2145,26 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std:
return sig;
}
RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, "$allconst");
cell->setParam("\\WIDTH", width);
cell->setPort("\\Y", sig);
cell->set_src_attribute(src);
return sig;
}
RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, "$allseq");
cell->setParam("\\WIDTH", width);
cell->setPort("\\Y", sig);
cell->set_src_attribute(src);
return sig;
}
RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID);

2
kernel/rtlil.h
View file

@ -1127,6 +1127,8 @@ public:
RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = "");
RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = "");
RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = "");
RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = "");
RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
};