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Add $allconst and $allseq cell types

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-02-23 13:14:47 +01:00
parent 2521ed305e
commit eb67a7532b
11 changed files with 67 additions and 9 deletions
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@ -387,15 +387,20 @@ Non-standard or SystemVerilog features for formal verification
- The system task ``$initstate`` evaluates to 1 in the initial state and
to 0 otherwise.
- The system task ``$anyconst`` evaluates to any constant value. This is
- The system function ``$anyconst`` evaluates to any constant value. This is
equivalent to declaring a reg as ``rand const``, but also works outside
of checkers. (Yosys also supports ``rand const`` outside checkers.)
- The system task ``$anyseq`` evaluates to any value, possibly a different
- The system function ``$anyseq`` evaluates to any value, possibly a different
value in each cycle. This is equivalent to declaring a reg as ``rand``,
but also works outside of checkers. (Yosys also supports ``rand``
variables outside checkers.)
- The system functions ``$allconst`` and ``$allseq`` are used to construct formal
exist-forall problems. Assertions are only violated if the trace vialoates
the assertion for all ``$allconst/$allseq`` values and assumptions only hold
if the trace satisfies the assumtion for all ``$allconst/$allseq`` values.
- The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
supported in any clocked block.