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example_synth: hardware mapping

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Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block.
Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section.
Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading).

Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.
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Krystine Sherwin 2024-01-08 16:59:03 +13:00
parent e6f8804e6a
commit eb5da87d52
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docs/source/code_examples/fifo/fifo.ys
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@ -65,7 +65,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdat
# ========================================================
memory -nomap
memory_collect
# or use the following commands:
# design -reset
# read_verilog fifo.v