mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-09-23 10:32:54 +02:00
parent 9659f7a99e
commit eb452ffb28
1 changed files with 9 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

12
frontends/verilog/verilog_parser.y
View file

@ -881,9 +881,15 @@ param_decl_list:
single_param_decl: single_param_decl:
TOK_ID '=' expr { TOK_ID '=' expr {
if (astbuf1 == nullptr) AstNode *node;
frontend_verilog_yyerror("syntax error"); if (astbuf1 == nullptr) {
AstNode *node = astbuf1->clone(); if (!sv_mode)
frontend_verilog_yyerror("syntax error");
node = new AstNode(AST_PARAMETER);
node->children.push_back(AstNode::mkconst_int(0, true));
} else {
node = astbuf1->clone();
}
node->str = *$1; node->str = *$1;
delete node->children[0]; delete node->children[0];
node->children[0] = $3; node->children[0] = $3;