mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 19:52:31 +00:00
Code Activity

Clean up pseudo-private member usage in frontends/ast/ast.cc.

Browse source
This commit is contained in:
Alberto Gonzalez 2020-03-19 06:15:53 +00:00
parent 0cbf102364
commit eb30d66d01
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 13 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

24
frontends/ast/ast.cc
View file

@ -1281,9 +1281,9 @@ AstNode * AST::find_modport(AstNode *intf, std::string name)
// Iterate over all wires in an interface and add them as wires in the AST module: // Iterate over all wires in an interface and add them as wires in the AST module:
void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport) void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport)
{ {
for (auto &wire_it : intfmodule->wires_){ for (auto w : intfmodule->wires()){
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
std::string origname = log_id(wire_it.first); std::string origname = log_id(w->name);
std::string newname = intfname + "." + origname; std::string newname = intfname + "." + origname;
wire->str = newname; wire->str = newname;
if (modport != NULL) { if (modport != NULL) {
@ -1326,9 +1326,9 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
for (auto &intf : local_interfaces) { for (auto &intf : local_interfaces) {
std::string intfname = intf.first.str(); std::string intfname = intf.first.str();
RTLIL::Module *intfmodule = intf.second; RTLIL::Module *intfmodule = intf.second;
for (auto &wire_it : intfmodule->wires_){ for (auto w : intfmodule->wires()){
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
std::string newname = log_id(wire_it.first); std::string newname = log_id(w->name);
newname = intfname + "." + newname; newname = intfname + "." + newname;
wire->str = newname; wire->str = newname;
new_ast->children.push_back(wire); new_ast->children.push_back(wire);
@ -1352,7 +1352,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
std::pair<std::string,std::string> res = split_modport_from_type(ch->str); std::pair<std::string,std::string> res = split_modport_from_type(ch->str);
std::string interface_type = res.first; std::string interface_type = res.first;
std::string interface_modport = res.second; // Is "", if no modport std::string interface_modport = res.second; // Is "", if no modport
if (design->modules_.count(interface_type) > 0) { if (design->module(interface_type) != nullptr) {
// Add a cell to the module corresponding to the interface port such that // Add a cell to the module corresponding to the interface port such that
// it can further propagated down if needed: // it can further propagated down if needed:
AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE); AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE);
@ -1362,7 +1362,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
new_ast->children.push_back(cell_for_intf); new_ast->children.push_back(cell_for_intf);
// Get all members of this non-overridden dummy interface instance: // Get all members of this non-overridden dummy interface instance:
RTLIL::Module *intfmodule = design->modules_[interface_type]; // All interfaces should at this point in time (assuming RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming
// reprocess_module is called from the hierarchy pass) be // reprocess_module is called from the hierarchy pass) be
// present in design->modules_ // present in design->modules_
AstModule *ast_module_of_interface = (AstModule*)intfmodule; AstModule *ast_module_of_interface = (AstModule*)intfmodule;
@ -1456,10 +1456,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
RTLIL::Module* mod = design->module(modname); RTLIL::Module* mod = design->module(modname);
// Now that the interfaces have been exploded, we can delete the dummy port related to every interface. // Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
pool<RTLIL::Wire*> to_remove;
for(auto &intf : interfaces) { for(auto &intf : interfaces) {
if(mod->wires_.count(intf.first)) { if(mod->wire(intf.first) != nullptr) {
mod->wires_.erase(intf.first); to_remove.insert(mod->wire(intf.first));
mod->fixup_ports();
// We copy the cell of the interface to the sub-module such that it can further be found if it is propagated // We copy the cell of the interface to the sub-module such that it can further be found if it is propagated
// down to sub-sub-modules etc. // down to sub-sub-modules etc.
RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name); RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name);
@ -1469,6 +1469,8 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str()); log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
} }
} }
mod->remove(to_remove);
mod->fixup_ports();
// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module': // If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
if (interfaces.size() > 0) { if (interfaces.size() > 0) {