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Merge branch 'xaig' into xc7mux

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This commit is contained in:
Eddie Hung 2019-05-31 13:03:03 -07:00
commit eb08e71bd1
5 changed files with 99 additions and 15 deletions
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6
passes/techmap/abc9.cc
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@ -537,11 +537,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
output_bits.insert({wire, i});
}
else {
//if (w->name == "\\__dummy_o__") {
// log("Don't call ABC as there is nothing to map.\n");
// goto cleanup;
//}
// Attempt another wideports_split here because there
// exists the possibility that different bits of a port
// could be an input and output, therefore parse_xaiger()
@ -752,7 +747,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// log("Don't call ABC as there is nothing to map.\n");
//}
cleanup:
if (cleanup)
{
log("Removing temp directory.\n");