From eae87b31612669ac5af4f3c466a65f6c74a2cc11 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 6 Oct 2025 14:39:25 +0200 Subject: [PATCH] WIP half broken snapshot --- kernel/rtlil.cc | 42 +-- kernel/rtlil.h | 49 +++ kernel/rtlil_bufnorm.cc | 504 +++++++++++++++++++++++++++++- passes/opt/Makefile.inc | 1 + passes/opt/opt_clean.cc | 12 +- passes/opt/opt_expr.cc | 45 ++- passes/opt/opt_merge.cc | 6 +- passes/opt/opt_merge_inc.cc | 608 ++++++++++++++++++++++++++++++++++++ passes/techmap/bufnorm.cc | 19 +- 9 files changed, 1226 insertions(+), 60 deletions(-) create mode 100644 passes/opt/opt_merge_inc.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8daf2c821..e5ce2b407 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1437,6 +1437,7 @@ RTLIL::Module::Module() RTLIL::Module::~Module() { + clear_sig_norm_index(); for (auto &pr : wires_) delete pr.second; for (auto &pr : memories) @@ -2842,24 +2843,6 @@ void RTLIL::Module::remove(const pool &wires) delete it; } } - -void RTLIL::Module::remove(RTLIL::Cell *cell) -{ - while (!cell->connections_.empty()) - cell->unsetPort(cell->connections_.begin()->first); - - log_assert(cells_.count(cell->name) != 0); - log_assert(refcount_cells_ == 0); - cells_.erase(cell->name); - if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) { - cell->type.clear(); - cell->name.clear(); - pending_deleted_cells.insert(cell); - } else { - delete cell; - } -} - void RTLIL::Module::remove(RTLIL::Process *process) { log_assert(processes.count(process->name) != 0); @@ -2996,29 +2979,6 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs connect(RTLIL::SigSig(lhs, rhs)); } -void RTLIL::Module::new_connections(const std::vector &new_conn) -{ - for (auto mon : monitors) - mon->notify_connect(this, new_conn); - - if (design) - for (auto mon : design->monitors) - mon->notify_connect(this, new_conn); - - if (yosys_xtrace) { - log("#X# New connections vector in %s:\n", log_id(this)); - for (auto &conn: new_conn) - log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first)); - log_backtrace("-X- ", yosys_xtrace-1); - } - - connections_ = new_conn; -} - -const std::vector &RTLIL::Module::connections() const -{ - return connections_; -} void RTLIL::Module::fixup_ports() { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 5271a3111..92ff1939b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -121,6 +121,7 @@ namespace RTLIL struct Binding; struct IdString; struct StaticIdString; + struct SigNormIndex; typedef std::pair SigSig; @@ -133,6 +134,8 @@ namespace RTLIL const IdString &id_str; const StaticId id; }; + + struct PortBit; }; struct RTLIL::IdString @@ -1527,7 +1530,9 @@ struct RTLIL::Design dict scratchpad; bool flagBufferedNormalized = false; + bool flagSigNormalized = false; void bufNormalize(bool enable=true); + void sigNormalize(bool enable=true); int refcount_modules_; dict modules_; @@ -1687,6 +1692,10 @@ struct RTLIL::Design struct RTLIL::Module : public RTLIL::NamedObject { + friend struct RTLIL::SigNormIndex; + friend struct RTLIL::Cell; + friend struct RTLIL::Design; + Hasher::hash_t hashidx_; [[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; } @@ -1745,6 +1754,18 @@ public: dict> buf_norm_connect_index; void bufNormalize(); +protected: + SigNormIndex *sig_norm_index = nullptr; + void clear_sig_norm_index(); + int timestamp_ = 0; +public: + void sigNormalize(); + + int timestamp() const { return timestamp_; } + int next_timestamp(); + std::vector dirty_cells(int starting_from); + const pool &fanout(SigBit bit); + template void rewrite_sigspecs(T &functor); template void rewrite_sigspecs2(T &functor); void cloneInto(RTLIL::Module *new_mod) const; @@ -2057,6 +2078,7 @@ struct RTLIL::Wire : public RTLIL::NamedObject protected: // use module->addWire() and module->remove() to create or destroy wires friend struct RTLIL::Module; + friend struct RTLIL::SigNormIndex; Wire(); ~Wire(); @@ -2248,6 +2270,33 @@ public: RTLIL::Process *clone() const; }; +struct RTLIL::PortBit +{ + RTLIL::Cell *cell; + RTLIL::IdString port; + int offset; + PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {} + + bool operator<(const PortBit &other) const { + if (cell != other.cell) + return cell < other.cell; + if (port != other.port) + return port < other.port; + return offset < other.offset; + } + + bool operator==(const PortBit &other) const { + return cell == other.cell && port == other.port && offset == other.offset; + } + + [[nodiscard]] Hasher hash_into(Hasher h) const { + h.eat(cell->name); + h.eat(port); + h.eat(offset); + return h; + } +}; + inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index 47a9b1edc..1a1529fcd 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -28,6 +28,219 @@ YOSYS_NAMESPACE_BEGIN +typedef std::pair cell_port_t; + + + +struct RTLIL::SigNormIndex +{ + SigNormIndex(RTLIL::Module *module) : module(module) {} + RTLIL::Module *module; + + SigMap sigmap; + size_t restored_connections = 0; + + dict> fanout; + + pool newly_driven; + + dict cell_timestamps; + dict> timestamp_cells; + pool dirty; + + void setup() { + module->fixup_ports(); + setup_module_inputs(); + setup_driven_wires(); + setup_fanout(); + } + + void normalize() { + flush_connections(); + flush_newly_driven(); + } + + void setup_module_inputs() { + std::vector cells_to_remove; + dict input_port_cells; + + for (auto cell : module->cells()) { + if (cell->type != ID($input_port)) + continue; + + auto const &sig_y = cell->getPort(ID::Y); + Wire *wire; + if (sig_y.is_wire() && (wire = sig_y.as_wire())->port_input && !wire->port_output && !input_port_cells.count(wire)) + input_port_cells.emplace(wire, cell); + else + cells_to_remove.push_back(cell); + + for (auto cell : cells_to_remove) + module->remove(cell); + } + + for (auto portname : module->ports) { + Wire *wire = module->wire(portname); + if (wire->port_input && !wire->port_output && !input_port_cells.count(wire)) { + Cell *cell = module->addCell(NEW_ID, ID($input_port)); + cell->setParam(ID::WIDTH, GetSize(wire)); + cell->setPort(ID::Y, wire); + input_port_cells.emplace(wire, cell); + } + } + + for (auto [wire, cell] : input_port_cells) { + wire->driverCell_ = cell; + wire->driverPort_ = ID::Y; + } + } + + void setup_driven_wires() { + for (auto cell : module->cells()) { + for (auto &[port, sig] : cell->connections_) { + if (cell->port_dir(port) == RTLIL::PD_INPUT) + continue; + if (sig.is_wire()) { + Wire * wire = sig.as_wire(); + + if (wire->driverCell_ == cell && wire->driverPort_ == port) + continue; + if (wire->driverCell_ == nullptr) { + wire->driverCell_ = cell; + wire->driverPort_ = port; + continue; + } + } + + Wire *wire = module->addWire(NEW_ID, GetSize(sig)); + wire->driverCell_ = cell; + wire->driverPort_ = port; + + module->connect(sig, wire); + sig = wire; + } + } + } + + + void setup_fanout() { + for (auto cell : module->cells()) { + for (auto &[port, sig] : cell->connections_) { + if (cell->port_dir(port) != RTLIL::PD_INPUT) + continue; + int i = 0; + for (auto bit : sig) + fanout[bit].insert(PortBit(cell, port, i++)); + } + } + } + + void flush_connections() { + std::vector connect_lhs; + std::vector connect_rhs; + + auto begin = module->connections_.begin() + restored_connections; + auto end = module->connections_.end(); + + for (auto it = begin; it != end; ++it) { + auto &[lhs, rhs] = *it; + sigmap.apply(lhs); + sigmap.apply(rhs); + auto rhs_bits = rhs.bits().begin(); + + connect_lhs.clear(); + connect_rhs.clear(); + + for (auto l : lhs.bits()) { + auto r = *(rhs_bits++); + if (l == r) + continue; + // TODO figure out what should happen with 'z + bool l_driven = !l.is_wire() || l.wire->known_driver(); + bool r_driven = !r.is_wire() || r.wire->known_driver(); + if (l_driven && r_driven) { + connect_lhs.push_back(l); + connect_rhs.push_back(r); + continue; + } + + sigmap.add(l, r); + if (l_driven) { + sigmap.database.promote(l); + newly_driven.insert(r); + } else { + sigmap.database.promote(r); + newly_driven.insert(l); + } + } + + if (!connect_lhs.empty()) { + Cell *cell = module->addCell(NEW_ID, ID($connect)); + cell->setParam(ID::WIDTH, GetSize(connect_lhs)); + cell->setPort(ID::A, std::move(connect_lhs)); + cell->setPort(ID::B, std::move(connect_rhs)); + } + } + + module->connections_.clear(); + restored_connections = 0; + } + + void flush_newly_driven() { + pool ports_to_normalize; + SigSpec tmp; + + while (!newly_driven.empty()) { + SigBit current = newly_driven.pop(); + + auto found = fanout.find(current); + if (found == fanout.end()) + continue; + + ports_to_normalize.clear(); + + for (auto const &portbit : found->second) + ports_to_normalize.emplace(portbit.cell, portbit.port); + + for (auto const &[cell, port] : ports_to_normalize) { + tmp = cell->getPort(port); + cell->setPort(port, tmp); + } + } + } + + void restore_connections() { + flush_connections(); + pool wires; + for (auto const &bit : sigmap.database) + if (bit.is_wire()) + wires.insert(bit.wire); + + + std::vector connect_lhs; + std::vector connect_rhs; + + for (auto wire : wires) { + connect_lhs.clear(); + connect_rhs.clear(); + for (int i = 0; i < GetSize(wire); ++i) { + SigBit l = SigBit(wire, i); + SigBit r = sigmap(l); + if (l == r) + continue; + connect_lhs.push_back(l); + connect_rhs.push_back(r); + } + + if (!connect_lhs.empty()) + module->connections_.emplace_back(std::move(connect_lhs), std::move(connect_rhs)); + } + + restored_connections = module->connections_.size(); + } +}; + + void RTLIL::Design::bufNormalize(bool enable) { if (!enable) @@ -50,6 +263,8 @@ void RTLIL::Design::bufNormalize(bool enable) return; } + log_assert(!flagSigNormalized); + if (!flagBufferedNormalized) { for (auto module : modules()) @@ -78,8 +293,190 @@ void RTLIL::Design::bufNormalize(bool enable) module->bufNormalize(); } +void RTLIL::Design::sigNormalize(bool enable) +{ + if (!enable) + { + if (!flagSigNormalized) + return; + + + for (auto module : modules()) { + module->connections(); + if (module->sig_norm_index != nullptr) { + delete module->sig_norm_index; + module->sig_norm_index = nullptr; + } + + for (auto wire : module->wires()) { + wire->driverCell_ = nullptr; + wire->driverPort_ = IdString(); + } + } + + flagSigNormalized = false; + return; + } + + log_assert(!flagBufferedNormalized); + + if (!flagSigNormalized) + { + + + flagSigNormalized = true; + } + + for (auto module : modules()) + module->sigNormalize(); +} + +void RTLIL::Module::sigNormalize() +{ + log_assert(design->flagSigNormalized); + + if (sig_norm_index == nullptr) { + auto new_index = new RTLIL::SigNormIndex(this); + new_index->setup(); + sig_norm_index = new_index; + } + + sig_norm_index->normalize(); + +} + +void RTLIL::Module::clear_sig_norm_index() +{ + if (sig_norm_index == nullptr) + return; + delete sig_norm_index; +} + + +const std::vector &RTLIL::Module::connections() const +{ + if (sig_norm_index != nullptr) + sig_norm_index->restore_connections(); + return connections_; +} + +void RTLIL::Module::new_connections(const std::vector &new_conn) +{ + if (sig_norm_index != nullptr) { + sig_norm_index->restore_connections(); + sig_norm_index->restored_connections = 0; + // TODO clear the sigmap as well? + } + for (auto mon : monitors) + mon->notify_connect(this, new_conn); + + if (design) + for (auto mon : design->monitors) + mon->notify_connect(this, new_conn); + + if (yosys_xtrace) { + log("#X# New connections vector in %s:\n", log_id(this)); + for (auto &conn: new_conn) + log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first)); + log_backtrace("-X- ", yosys_xtrace-1); + } + + connections_ = new_conn; +} + + +int RTLIL::Module::next_timestamp() +{ + int old = timestamp_; + int current = timestamp_ = old + 1; + + if (sig_norm_index != nullptr) { + sigNormalize(); + for (auto cell : sig_norm_index->dirty) { + auto [found, inserted] = sig_norm_index->cell_timestamps.emplace(cell, old); + if (!inserted) { + log_assert(found->second != old); + auto found_cells = sig_norm_index->timestamp_cells.find(found->second); + log_assert(found_cells != sig_norm_index->timestamp_cells.end()); + bool erased = found_cells->second.erase(cell); + log_assert(erased); + if (found_cells->second.empty()) + sig_norm_index->timestamp_cells.erase(found_cells); + found->second = old; + } + } + sig_norm_index->timestamp_cells[old] = std::move(sig_norm_index->dirty); + sig_norm_index->dirty.clear(); + } + + + return current; +} + + +std::vector RTLIL::Module::dirty_cells(int starting_from) +{ + sigNormalize(); + std::vector result; + if (starting_from == INT_MIN) { + result.reserve(cells_.size()); + for (auto cell : cells()) + result.push_back(cell); + return result; + } + + for (int i = starting_from; i < timestamp_; ++i) { + auto found = sig_norm_index->timestamp_cells.find(i); + if (found != sig_norm_index->timestamp_cells.end()) + for (auto cell : found->second) + result.push_back(cell); + } + if (starting_from <= timestamp_) + for (auto cell : sig_norm_index->dirty) + result.push_back(cell); + + return result; +} + +const pool &RTLIL::Module::fanout(SigBit bit) { + log_assert(sig_norm_index != nullptr); + auto found = sig_norm_index->fanout.find(bit); + static pool empty; + if (found == sig_norm_index->fanout.end()) + return empty; + return found->second; +} + +void RTLIL::Module::remove(RTLIL::Cell *cell) +{ + while (!cell->connections_.empty()) + cell->unsetPort(cell->connections_.begin()->first); + + log_assert(cells_.count(cell->name) != 0); + log_assert(refcount_cells_ == 0); + cells_.erase(cell->name); + if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) { + cell->type.clear(); + cell->name.clear(); + pending_deleted_cells.insert(cell); + } else { + if (sig_norm_index != nullptr) { + auto found = sig_norm_index->cell_timestamps.find(cell); + if (found != sig_norm_index->cell_timestamps.end()) { + auto found_cells = sig_norm_index->timestamp_cells.find(found->second); + log_assert(found_cells != sig_norm_index->timestamp_cells.end()); + bool erased = found_cells->second.erase(cell); + log_assert(erased); + if (found_cells->second.empty()) + sig_norm_index->timestamp_cells.erase(found_cells); + sig_norm_index->cell_timestamps.erase(found); + } + sig_norm_index->dirty.erase(cell); + } + delete cell; + } +} -typedef ModWalker::PortBit PortBit; void RTLIL::Module::bufNormalize() { @@ -540,6 +937,53 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) log_backtrace("-X- ", yosys_xtrace-1); } + if (module->sig_norm_index != nullptr) { + module->sig_norm_index->dirty.insert(this); + bool is_input_port = port_dir(portname) == RTLIL::PD_INPUT; + if (is_input_port) { + auto &fanout = module->sig_norm_index->fanout; + int counter = 0; + for (auto bit : conn_it->second) { + int i = counter++; + auto found = fanout.find(bit); + log_assert(found != fanout.end()); + int erased = found->second.erase(PortBit(this, portname, i)); + log_assert(erased); + if (found->second.empty()) + fanout.erase(found); + } + } else { + Wire *w = conn_it->second.as_wire(); + log_assert(w->driverCell_ == this); + log_assert(w->driverPort_ == portname); + w->driverCell_ = nullptr; + w->driverPort_ = IdString(); + } + // bool clear_fanout = true; + // if (conn_it->second.is_wire()) { + // Wire *w = conn_it->second.as_wire(); + // if (w->driverCell_ == this && w->driverPort_ == portname) { + // w->driverCell_ = nullptr; + // w->driverPort_ = IdString(); + // clear_fanout = false; + // } + // } + + // if (clear_fanout) { + // auto &fanout = module->sig_norm_index->fanout; + // int counter = 0; + // for (auto bit : conn_it->second) { + // int i = counter++; + // auto found = fanout.find(bit); + // log_assert(found != fanout.end()); + // int erased = found->second.erase(PortBit(this, portname, i)); + // log_assert(erased); + // if (found->second.empty()) + // fanout.erase(found); + // } + // } + } + if (module->design && module->design->flagBufferedNormalized) { if (conn_it->second.is_wire()) { Wire *w = conn_it->second.as_wire(); @@ -583,6 +1027,25 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal) { + bool is_input_port = false; + if (module->sig_norm_index != nullptr) { + module->sig_norm_index->sigmap.apply(signal); + auto dir = port_dir(portname); + + if (dir == RTLIL::PD_INPUT) { + is_input_port = true; + } else { + Wire *wire = nullptr; + if (signal.is_wire() && (wire = signal.as_wire())->driverCell_ != nullptr) + wire = nullptr; + if (wire == nullptr) { + wire = module->addWire(NEW_ID, GetSize(signal)); + module->connect(signal, wire); + signal = wire; + } + } + } + auto r = connections_.insert(portname); auto conn_it = r.first; if (!r.second && conn_it->second == signal) @@ -600,6 +1063,45 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal log_backtrace("-X- ", yosys_xtrace-1); } + + if (module->sig_norm_index != nullptr) { + module->sig_norm_index->dirty.insert(this); + if (!r.second) { + if (is_input_port) { + auto &fanout = module->sig_norm_index->fanout; + int counter = 0; + for (auto bit : conn_it->second) { + int i = counter++; + auto found = fanout.find(bit); + log_assert(found != fanout.end()); + int erased = found->second.erase(PortBit(this, portname, i)); + log_assert(erased); + if (found->second.empty()) + fanout.erase(found); + } + } else { + Wire *w = conn_it->second.as_wire(); + log_assert(w->driverCell_ == this); + log_assert(w->driverPort_ == portname); + w->driverCell_ = nullptr; + w->driverPort_ = IdString(); + } + } + + if (is_input_port) { + auto &fanout = module->sig_norm_index->fanout; + int i = 0; + for (auto bit : signal) + fanout[bit].insert(PortBit(this, portname, i++)); + } else { + Wire *w = signal.as_wire(); + log_assert(w->driverCell_ == nullptr); + log_assert(w->driverPort_.empty()); + w->driverCell_ = this; + w->driverPort_ = portname; + } + } + if (module->design && module->design->flagBufferedNormalized) { // We eagerly clear a driver that got disconnected by changing this port connection diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 426d9a79a..7dddc67d5 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -1,6 +1,7 @@ OBJS += passes/opt/opt.o OBJS += passes/opt/opt_merge.o +OBJS += passes/opt/opt_merge_inc.o OBJS += passes/opt/opt_mem.o OBJS += passes/opt/opt_mem_feedback.o OBJS += passes/opt/opt_mem_priority.o diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 996a9b3c9..a9f98fd4a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -507,8 +507,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (verbose && del_temp_wires_count) log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count); - if (!del_wires_queue.empty()) - module->design->scratchpad_set_bool("opt.did_something", true); + // if (!del_wires_queue.empty()) + // module->design->scratchpad_set_bool("opt.did_something", true); return !del_wires_queue.empty(); } @@ -600,6 +600,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool log("Finding unused cells or wires in module %s..\n", module->name); std::vector delcells; + bool did_something_here = false; for (auto cell : module->cells()) { if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) { bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool(); @@ -623,6 +624,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool if (!y.empty()) module->connect(y, a); delcells.push_back(cell); + did_something_here = true; } else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) { RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec b = cell->getPort(ID::B); @@ -648,7 +650,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool } module->remove(cell); } - if (!delcells.empty()) + if (did_something_here) module->design->scratchpad_set_bool("opt.did_something", true); rmunused_module_cells(module, verbose); @@ -694,6 +696,8 @@ struct OptCleanPass : public Pass { } extra_args(args, argidx, design); + design->sigNormalize(false); + keep_cache.reset(design, purge_mode); ct_reg.setup_internals_mem(); @@ -756,6 +760,8 @@ struct CleanPass : public Pass { } extra_args(args, argidx, design); + design->sigNormalize(false); + keep_cache.reset(design); ct_reg.setup_internals_mem(); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 86d96ea7a..721938050 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -393,12 +393,15 @@ int get_highest_hot_index(RTLIL::SigSpec signal) return -1; } -void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv) +void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv, int timestamp=INT_MIN) { - SigMap assign_map(module); + SigMap assign_map; //(module); dict invert_map; - for (auto cell : module->cells()) { + + auto dirty_cells = module->dirty_cells(timestamp); + + for (auto cell : dirty_cells) { if (design->selected(module, cell) && cell->type[0] == '$') { if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) @@ -413,7 +416,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons ct_memcells.setup_stdcells_mem(); if (!noclkinv) - for (auto cell : module->cells()) + for (auto cell : dirty_cells) if (design->selected(module, cell)) { if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2))) handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map); @@ -491,9 +494,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } TopoSort> cells; + dict outbit_to_cell; - for (auto cell : module->cells()) + for (auto cell : dirty_cells) if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) { for (auto &conn : cell->connections()) if (yosys_celltypes.cell_output(cell->type, conn.first)) @@ -502,7 +506,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cells.node(cell); } - for (auto cell : module->cells()) + for (auto cell : dirty_cells) if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) { const int r_index = cells.node(cell); for (auto &conn : cell->connections()) @@ -518,6 +522,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module)); } + log("iterating over %d cells\n", GetSize(cells.sorted)); + for (auto cell : cells.sorted) { #define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) @@ -1171,10 +1177,10 @@ skip_fine_alu: if (input.match("01 ")) ACTION_DO(ID::Y, input.extract(0, 1)); if (input.match("10 ")) { cover("opt.opt_expr.mux_to_inv"); - cell->type = ID($_NOT_); cell->setPort(ID::A, input.extract(0, 1)); cell->unsetPort(ID::B); cell->unsetPort(ID::S); + cell->type = ID($_NOT_); goto next_cell; } if (input.match("11 ")) ACTION_DO_Y(1); @@ -1275,10 +1281,10 @@ skip_fine_alu: } else { cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); - cell->type = ID($not); cell->parameters.erase(ID::B_WIDTH); cell->parameters.erase(ID::B_SIGNED); cell->unsetPort(ID::B); + cell->type = ID($not); did_something = true; } goto next_cell; @@ -1291,7 +1297,7 @@ skip_fine_alu: cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell), log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool"); - cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); + if (assign_map(cell->getPort(ID::A)).is_fully_zero()) { cell->setPort(ID::A, cell->getPort(ID::B)); cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED)); @@ -1300,6 +1306,7 @@ skip_fine_alu: cell->unsetPort(ID::B); cell->unsetParam(ID::B_SIGNED); cell->unsetParam(ID::B_WIDTH); + cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); did_something = true; goto next_cell; } @@ -1449,10 +1456,10 @@ skip_fine_alu: cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED)); } - cell->type = arith_inverse ? ID($neg) : ID($pos); cell->unsetPort(ID::B); cell->parameters.erase(ID::B_WIDTH); cell->parameters.erase(ID::B_SIGNED); + cell->type = arith_inverse ? ID($neg) : ID($pos); cell->check(); did_something = true; @@ -2358,9 +2365,16 @@ struct OptExprPass : public Pass { } extra_args(args, argidx, design); + design->sigNormalize(true); + + + CellTypes ct(design); for (auto module : design->selected_modules()) { + + int replace_const_cells_timestamp = INT_MIN; + int replace_const_cells_consume_x_timestamp = INT_MIN; log("Optimizing module %s.\n", log_id(module)); if (undriven) { @@ -2373,12 +2387,17 @@ struct OptExprPass : public Pass { do { do { did_something = false; - replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv); + module->next_timestamp(); + replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv, replace_const_cells_timestamp); + replace_const_cells_timestamp = module->timestamp(); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); - if (!keepdc) - replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv); + if (!keepdc) { + module->next_timestamp(); + replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv, replace_const_cells_consume_x_timestamp); + replace_const_cells_consume_x_timestamp = module->timestamp(); + } if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 6cdcbc822..96758fd74 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -284,6 +284,8 @@ struct OptMergeWorker CellPtrHash, CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this)); + log("scanning %d cells\n", GetSize(cells)); + int iter_count = 0; for (auto cell : cells) { auto [cell_in_map, inserted] = known_cells.insert(cell); @@ -316,8 +318,10 @@ struct OptMergeWorker log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); module->remove(cell); total_count++; + iter_count++; } } + log("removed %d cells\n", iter_count); } log_suppressed(); @@ -325,7 +329,7 @@ struct OptMergeWorker }; struct OptMergePass : public Pass { - OptMergePass() : Pass("opt_merge", "consolidate identical cells") { } + OptMergePass() : Pass("opt_merge_old", "consolidate identical cells") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/opt/opt_merge_inc.cc b/passes/opt/opt_merge_inc.cc new file mode 100644 index 000000000..d0735efff --- /dev/null +++ b/passes/opt/opt_merge_inc.cc @@ -0,0 +1,608 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/ffinit.h" +#include "kernel/sigtools.h" +#include "kernel/log.h" +#include "kernel/celltypes.h" +#include "libs/sha1/sha1.h" +#include +#include +#include +#include +#include +#include + + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +template +inline Hasher hash_pair(const T &t, const U &u) { return hash_ops>::hash(t, u); } + +struct OptMergeIncWorker +{ + RTLIL::Design *design; + RTLIL::Module *module; + SigMap assign_map; + FfInitVals initvals; + bool mode_share_all; + + CellTypes ct; + int total_count; + + static Hasher hash_pmux_in(const SigSpec& sig_s, const SigSpec& sig_b, Hasher h) + { + int s_width = GetSize(sig_s); + int width = GetSize(sig_b) / s_width; + + hashlib::commutative_hash comm; + for (int i = 0; i < s_width; i++) + comm.eat(hash_pair(sig_s[i], sig_b.extract(i*width, width))); + + return comm.hash_into(h); + } + + static void sort_pmux_conn(dict &conn) + { + SigSpec sig_s = conn.at(ID::S); + SigSpec sig_b = conn.at(ID::B); + + int s_width = GetSize(sig_s); + int width = GetSize(sig_b) / s_width; + + vector> sb_pairs; + for (int i = 0; i < s_width; i++) + sb_pairs.push_back(pair(sig_s[i], sig_b.extract(i*width, width))); + + std::sort(sb_pairs.begin(), sb_pairs.end()); + + conn[ID::S] = SigSpec(); + conn[ID::B] = SigSpec(); + + for (auto &it : sb_pairs) { + conn[ID::S].append(it.first); + conn[ID::B].append(it.second); + } + } + + Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h) const + { + // TODO: when implemented, use celltypes to match: + // (builtin || stdcell) && (unary || binary) && symmetrical + if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), + ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) { + hashlib::commutative_hash comm; + comm.eat((cell->getPort(ID::A))); + comm.eat((cell->getPort(ID::B))); + h = comm.hash_into(h); + } else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { + SigSpec a = (cell->getPort(ID::A)); + a.sort(); + h = a.hash_into(h); + } else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { + SigSpec a = (cell->getPort(ID::A)); + a.sort_and_unify(); + h = a.hash_into(h); + } else if (cell->type == ID($pmux)) { + SigSpec sig_s = (cell->getPort(ID::S)); + SigSpec sig_b = (cell->getPort(ID::B)); + h = hash_pmux_in(sig_s, sig_b, h); + h = (cell->getPort(ID::A)).hash_into(h); + } else { + hashlib::commutative_hash comm; + for (const auto& [port, sig] : cell->connections()) { + if (cell->output(port)) + continue; + comm.eat(hash_pair(port, (sig))); + } + h = comm.hash_into(h); + if (cell->is_builtin_ff()) + h = initvals(cell->getPort(ID::Q)).hash_into(h); + } + return h; + } + + static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h) + { + hashlib::commutative_hash comm; + for (const auto& param : cell->parameters) { + comm.eat(param); + } + return comm.hash_into(h); + } + + Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h) const + { + h.eat(cell->type); + h = hash_cell_inputs(cell, h); + h = hash_cell_parameters(cell, h); + return h; + } + + bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const + { + if (cell1 == cell2) return true; + if (cell1->type != cell2->type) return false; + + if (cell1->parameters != cell2->parameters) + return false; + + if (cell1->connections_.size() != cell2->connections_.size()) + return false; + for (const auto &it : cell1->connections_) + if (!cell2->connections_.count(it.first)) + return false; + + decltype(Cell::connections_) conn1, conn2; + conn1.reserve(cell1->connections_.size()); + conn2.reserve(cell1->connections_.size()); + + for (const auto &it : cell1->connections_) { + if (cell1->output(it.first)) { + if (it.first == ID::Q && cell1->is_builtin_ff()) { + // For the 'Q' output of state elements, + // use the (* init *) attribute value + conn1[it.first] = initvals(it.second); + conn2[it.first] = initvals(cell2->getPort(it.first)); + } + else { + conn1[it.first] = RTLIL::SigSpec(); + conn2[it.first] = RTLIL::SigSpec(); + } + } + else { + conn1[it.first] = (it.second); + conn2[it.first] = (cell2->getPort(it.first)); + } + } + + if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), + ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) { + if (conn1.at(ID::A) < conn1.at(ID::B)) { + std::swap(conn1[ID::A], conn1[ID::B]); + } + if (conn2.at(ID::A) < conn2.at(ID::B)) { + std::swap(conn2[ID::A], conn2[ID::B]); + } + } else + if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) { + conn1[ID::A].sort(); + conn2[ID::A].sort(); + } else + if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { + conn1[ID::A].sort_and_unify(); + conn2[ID::A].sort_and_unify(); + } else + if (cell1->type == ID($pmux)) { + sort_pmux_conn(conn1); + sort_pmux_conn(conn2); + } + + return conn1 == conn2; + } + + bool has_dont_care_initval(const RTLIL::Cell *cell) + { + if (!cell->is_builtin_ff()) + return false; + + return !initvals(cell->getPort(ID::Q)).is_fully_def(); + } + + OptMergeIncWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all, bool mode_keepdc) : + design(design), module(module), mode_share_all(mode_share_all) + { + total_count = 0; + ct.setup_internals(); + ct.setup_internals_mem(); + ct.setup_stdcells(); + ct.setup_stdcells_mem(); + + if (mode_nomux) { + ct.cell_types.erase(ID($mux)); + ct.cell_types.erase(ID($pmux)); + } + + ct.cell_types.erase(ID($tribuf)); + ct.cell_types.erase(ID($_TBUF_)); + ct.cell_types.erase(ID($anyseq)); + ct.cell_types.erase(ID($anyconst)); + ct.cell_types.erase(ID($allseq)); + ct.cell_types.erase(ID($allconst)); + ct.cell_types.erase(ID($connect)); + ct.cell_types.erase(ID($input_port)); + + log("Finding identical cells in module `%s'.\n", module->name); + assign_map.set(module); + + initvals.set(&assign_map, module); + + + // We keep a set of known cells. They're hashed with our hash_cell_function + // and compared with our compare_cell_parameters_and_connections. + // Both need to capture OptMergeIncWorker to access initvals + struct CellPtrHash { + const OptMergeIncWorker& worker; + CellPtrHash(const OptMergeIncWorker& w) : worker(w) {} + std::size_t operator()(const Cell* c) const { + return (std::size_t)worker.hash_cell_function(c, Hasher()).yield(); + } + }; + struct CellPtrEqual { + const OptMergeIncWorker& worker; + CellPtrEqual(const OptMergeIncWorker& w) : worker(w) {} + bool operator()(const Cell* lhs, const Cell* rhs) const { + return worker.compare_cell_parameters_and_connections(lhs, rhs); + } + }; + // std::unordered_set< + // RTLIL::Cell*, + // CellPtrHash, + // CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this)); + + dict hashes; + dict first_with_hash; + dict> more_with_hash; + + auto forget_cell = [&](Cell * cell) { + auto found = hashes.find(cell); + if (found != hashes.end()) { + auto found_first = first_with_hash.find(found->second); + log_assert(found_first != first_with_hash.end()); + auto found_more = more_with_hash.find(found->second); + if (found_more != more_with_hash.end()) { + found_more->second.erase(cell); + found_first->second = *found_more->second.begin(); + if (found_more->second.size() < 2) + more_with_hash.erase(found_more); + } + + // auto found_first = first_with_hash.find(found->second); + // log_assert(found_first != first_with_hash.end()); + // if (found_first->second == cell) { + // auto found_more = more_with_hash.find(found->second); + // if (found_more != more_with_hash.end()) { + // log_assert(!found_more->second.empty()); + // found_first->second = found_more->second.pop(); + // if (found_more->second.empty()) + // more_with_hash.erase(found_more); + + // } else { + // first_with_hash.erase(found_first); + // } + + // } else { + // auto found_more = more_with_hash.find(found->second); + // if (found_more != more_with_hash.end()) { + // found_more->second.erase(cell); + // if (found_more->second.empty()) + // more_with_hash.erase(found_more); + // } + // } + } + }; + + auto remember_cell = [&](Cell * cell, uint32_t hash) -> bool { + hashes[cell] = hash; + auto [it, inserted] = first_with_hash.emplace(hash, cell); + if (!inserted) { + auto &more = more_with_hash[hash]; + if (more.empty()) + more.emplace(it->second); + more.emplace(cell); + } + return !inserted; + }; + + int timestamp = INT_MIN; + + bool did_something = true; + // A cell may have to go through a lot of collisions if the hash + // function is performing poorly, but it's a symptom of something bad + // beyond the user's control. + + bool first = true; + while (did_something) + { + std::vector cells; + + if (timestamp == INT_MIN) { + timestamp = module->next_timestamp(); + cells.reserve(module->cells().size()); + for (auto cell : module->cells()) { + if (!design->selected(module, cell)) + continue; + if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) { + // Ignore those for performance: meminit can have an excessively large port, + // mem can have an excessively large parameter holding the init data + continue; + } + if (cell->type == ID($scopeinfo)) + continue; + if (mode_keepdc && has_dont_care_initval(cell)) + continue; + if (!cell->known()) + continue; + if (!mode_share_all && !ct.cell_known(cell->type)) + continue; + + cells.push_back(cell); + } + } else { + int next = module->next_timestamp(); + // idict pending; + // for (auto cell : module->dirty_cells(timestamp)) + // pending(cell); + // std::vector *> fanouts; + // int i = 0; + // while (i < GetSize(pending)) { + // Cell * cell = pending[i]; + pool pending; + for (auto cell : module->dirty_cells(timestamp)) { + if (!design->selected(module, cell)) + continue; + if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) { + // Ignore those for performance: meminit can have an excessively large port, + // mem can have an excessively large parameter holding the init data + continue; + } + if (cell->type == ID($scopeinfo)) + continue; + if (mode_keepdc && has_dont_care_initval(cell)) + continue; + if (!cell->known()) + continue; + if (!mode_share_all && !ct.cell_known(cell->type)) + continue; + + + cells.push_back(cell); + } + timestamp = next; + } + log("scanning %d cells\n", GetSize(cells)); + + did_something = false; + + if (!first) + for (auto cell : cells) + forget_cell(cell); + first = false; + + + pool buckets; + + for (auto cell : cells) { + uint32_t hash = hash_cell_function(cell, Hasher()).yield(); + if (remember_cell(cell, hash)) + buckets.emplace(hash); + } + + std::vector> pairs; + pool removed; + + log("scanning %d/%d/%d buckets\n", GetSize(buckets), GetSize(more_with_hash), GetSize(first_with_hash)); + for (auto hash : buckets) { + auto more = more_with_hash.at(hash); + + for (int i = 0; i < GetSize(more); ++i) { + for (int j = i + 1; j < GetSize(more); ++j) { + Cell *other_cell = *more.element(j); + if (removed.count(other_cell)) + continue; + Cell *cell = *more.element(i); + if (removed.count(cell)) + break; + + if (!compare_cell_parameters_and_connections(cell, other_cell)) + continue; + + if (cell->has_keep_attr()) { + if (other_cell->has_keep_attr()) + continue; + std::swap(cell, other_cell); + } + + removed.insert(cell); + pairs.emplace_back(other_cell, cell); + } + + } + } + + for (auto cell : removed) + forget_cell(cell); + + int iter_count = 0; + + for (auto [other_cell, cell] : pairs) { + did_something = true; + log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name); + + for (auto &[port, sig] : cell->connections()) { + if (cell->output(port)) { + module->connect(sig, other_cell->getPort(port)); + } + } + + log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); + module->remove(cell); + total_count++; + iter_count++; + } + log("removed %d cells\n", iter_count); + + + // hashes[cell] = hash; + + // auto [found, inserted] = first_with_hash.emplace(hash, cell); + + // if (inserted) { + // hashes.emplace(cell, hash); + // continue; + // } + + + // // if (check_candidate(found->second)) + // // continue; + + // auto found_more = more_with_hash[hash]; + + // // for (auto other_cell : found_more) { + // // if (check_candidate(other_cell)) + // // continue; + // // } + + // found_more.emplace(cell); + // hashes.emplace(cell, hash); + + // // if (compare_cell_parameters_and_connections(found->second, cell)) { + + // // } + + + // auto check_candidate = [&](Cell *other_cell) -> bool { + // if (!compare_cell_parameters_and_connections(other_cell, cell)) + // return false; + + // if (cell->has_keep_attr()) + // if (other_cell->has_keep_attr()) + // return false; + + // forget_cell(cell); + + + + // return true; + + // }; + + // if (!check_candidate(found->second)) { + // } + + + // for () + + + // auto [cell_in_map, inserted] = known_cells.insert(cell); + // if (!inserted) { + // // We've failed to insert since we already have an equivalent cell + // Cell* other_cell = *cell_in_map; + // if (cell->has_keep_attr()) { + // if (other_cell->has_keep_attr()) + // continue; + // known_cells.erase(other_cell); + // known_cells.insert(cell); + // std::swap(other_cell, cell); + // } + + // did_something = true; + // log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name); + // for (auto &it : cell->connections()) { + // if (cell->output(it.first)) { + // RTLIL::SigSpec other_sig = other_cell->getPort(it.first); + // log_debug(" Redirecting output %s: %s = %s\n", it.first, + // log_signal(it.second), log_signal(other_sig)); + // Const init = initvals(other_sig); + // initvals.remove_init(it.second); + // initvals.remove_init(other_sig); + // module->connect(RTLIL::SigSig(it.second, other_sig)); + // assign_map.add(it.second, other_sig); + // initvals.set_init(other_sig, init); + // } + // } + // log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); + // module->remove(cell); + // total_count++; + // } + + } + + log_suppressed(); + } +}; + +struct OptMergeIncPass : public Pass { + OptMergeIncPass() : Pass("opt_merge", "consolidate identical cells") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" opt_merge_inc [options] [selection]\n"); + log("\n"); + log("This pass identifies cells with identical type and input signals. Such cells\n"); + log("are then merged to one cell.\n"); + log("\n"); + log(" -nomux\n"); + log(" Do not merge MUX cells.\n"); + log("\n"); + log(" -share_all\n"); + log(" Operate on all cell types, not just built-in types.\n"); + log("\n"); + log(" -keepdc\n"); + log(" Do not merge flipflops with don't-care bits in their initial value.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing OPT_MERGE_INC pass (detect identical cells).\n"); + + bool mode_nomux = false; + bool mode_share_all = false; + bool mode_keepdc = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + std::string arg = args[argidx]; + if (arg == "-nomux") { + mode_nomux = true; + continue; + } + if (arg == "-share_all") { + mode_share_all = true; + continue; + } + if (arg == "-keepdc") { + mode_keepdc = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + design->sigNormalize(true); + + int total_count = 0; + for (auto module : design->selected_modules()) { + OptMergeIncWorker worker(design, module, mode_nomux, mode_share_all, mode_keepdc); + total_count += worker.total_count; + } + + + // design->sigNormalize(false); + + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); + log("Removed a total of %d cells.\n", total_count); + } +} OptMergeIncPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index a4552c71b..59f295765 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -94,8 +94,11 @@ struct BufnormPass : public Pass { log(" -update\n"); log(" Enter 'buffered-normalized mode' and (re-)normalize.\n"); log("\n"); + log(" -signorm\n"); + log(" Enter 'signal-normalized mode' and (re-)normalize.\n"); + log("\n"); log(" -reset\n"); - log(" Leave 'buffered-normalized mode' without changing the netlist.\n"); + log(" Leave '{buffered,signal}-normalized mode' without changing the netlist.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -116,6 +119,7 @@ struct BufnormPass : public Pass { bool conn_mode = false; bool update_mode = false; + bool signorm_mode = false; bool reset_mode = false; bool got_non_update_reset_opt = false; @@ -198,6 +202,10 @@ struct BufnormPass : public Pass { update_mode = true; continue; } + if (arg == "-signorm") { + signorm_mode = true; + continue; + } if (arg == "-reset") { reset_mode = true; continue; @@ -221,6 +229,9 @@ struct BufnormPass : public Pass { if (update_mode && got_non_update_reset_opt) log_cmd_error("Option -update can't be mixed with other options.\n"); + if (signorm_mode && got_non_update_reset_opt) + log_cmd_error("Option -signorm can't be mixed with other options.\n"); + if (reset_mode && got_non_update_reset_opt) log_cmd_error("Option -reset can't be mixed with other options.\n"); @@ -229,8 +240,14 @@ struct BufnormPass : public Pass { return; } + if (signorm_mode) { + design->sigNormalize(); + return; + } + if (reset_mode) { design->bufNormalize(false); + design->sigNormalize(false); return; }