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Use ID::keep more liberally too

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This commit is contained in:
Eddie Hung 2019-08-15 14:51:12 -07:00
parent 52355f5185
commit eae5a6b12c
10 changed files with 19 additions and 19 deletions
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4
passes/opt/muxpack.cc
View file

@ -135,7 +135,7 @@ struct MuxpackWorker
{ {
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->port_output || wire->get_bool_attribute(ID(keep))) { if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire))
sigbit_with_non_chain_users.insert(bit); sigbit_with_non_chain_users.insert(bit);
} }
@ -143,7 +143,7 @@ struct MuxpackWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID(keep))) if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
{ {
SigSpec a_sig = sigmap(cell->getPort(ID::A)); SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec b_sig; SigSpec b_sig;

8
passes/opt/opt_clean.cc
View file

@ -52,7 +52,7 @@ struct keep_cache_t
return cache.at(module); return cache.at(module);
cache[module] = true; cache[module] = true;
if (!module->get_bool_attribute(ID(keep))) { if (!module->get_bool_attribute(ID::keep)) {
bool found_keep = false; bool found_keep = false;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (query(cell)) found_keep = true; if (query(cell)) found_keep = true;
@ -122,7 +122,7 @@ void rmunused_module_cells(Module *module, bool verbose)
for (auto &it : module->wires_) { for (auto &it : module->wires_) {
Wire *wire = it.second; Wire *wire = it.second;
if (wire->port_output || wire->get_bool_attribute(ID(keep))) { if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire))
for (auto c : wire2driver[bit]) for (auto c : wire2driver[bit])
queue.insert(c), unused.erase(c); queue.insert(c), unused.erase(c);
@ -297,7 +297,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (!wire->port_input) if (!wire->port_input)
used_signals_nodrivers.add(sig); used_signals_nodrivers.add(sig);
} }
if (wire->get_bool_attribute(ID(keep))) { if (wire->get_bool_attribute(ID::keep)) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire); RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
assign_map.apply(sig); assign_map.apply(sig);
used_signals.add(sig); used_signals.add(sig);
@ -323,7 +323,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->port_id == 0) if (wire->port_id == 0)
goto delete_this_wire; goto delete_this_wire;
} else } else
if (wire->port_id != 0 || wire->get_bool_attribute(ID(keep)) || !initval.is_fully_undef()) { if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires // do not delete anything with "keep" or module ports or initialized wires
} else } else
if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) { if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {

2
passes/opt/opt_expr.cc
View file

@ -61,7 +61,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
} }
if (wire->port_input) if (wire->port_input)
driven_signals.add(sigmap(wire)); driven_signals.add(sigmap(wire));
if (wire->port_output || wire->get_bool_attribute(ID(keep))) if (wire->port_output || wire->get_bool_attribute(ID::keep))
used_signals.add(sigmap(wire)); used_signals.add(sigmap(wire));
all_signals.add(sigmap(wire)); all_signals.add(sigmap(wire));
} }

2
passes/opt/opt_lut.cc
View file

@ -104,7 +104,7 @@ struct OptLutWorker
if (cell->has_keep_attr()) if (cell->has_keep_attr())
continue; continue;
SigBit lut_output = cell->getPort(ID::Y); SigBit lut_output = cell->getPort(ID::Y);
if (lut_output.wire->get_bool_attribute(ID(keep))) if (lut_output.wire->get_bool_attribute(ID::keep))
continue; continue;
int lut_width = cell->getParam(ID(WIDTH)).as_int(); int lut_width = cell->getParam(ID(WIDTH)).as_int();

2
passes/opt/opt_muxtree.cc
View file

@ -137,7 +137,7 @@ struct OptMuxtreeWorker
} }
} }
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (wire->port_output || wire->get_bool_attribute(ID(keep))) if (wire->port_output || wire->get_bool_attribute(ID::keep))
for (int idx : sig2bits(RTLIL::SigSpec(wire))) for (int idx : sig2bits(RTLIL::SigSpec(wire)))
bit2info[idx].seen_non_mux = true; bit2info[idx].seen_non_mux = true;
} }

2
passes/opt/wreduce.cc
View file

@ -398,7 +398,7 @@ struct WreduceWorker
SigMap init_attr_sigmap = mi.sigmap; SigMap init_attr_sigmap = mi.sigmap;
for (auto w : module->wires()) { for (auto w : module->wires()) {
if (w->get_bool_attribute(ID(keep))) if (w->get_bool_attribute(ID::keep))
for (auto bit : mi.sigmap(w)) for (auto bit : mi.sigmap(w))
keep_bits.insert(bit); keep_bits.insert(bit);
if (w->attributes.count(ID(init))) { if (w->attributes.count(ID(init))) {

4
passes/techmap/abc.cc
View file

@ -198,7 +198,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (keepff) if (keepff)
for (auto &c : sig_q.chunks()) for (auto &c : sig_q.chunks())
if (c.wire != NULL) if (c.wire != NULL)
c.wire->attributes[ID(keep)] = 1; c.wire->attributes[ID::keep] = 1;
assign_map.apply(sig_d); assign_map.apply(sig_d);
assign_map.apply(sig_q); assign_map.apply(sig_q);
@ -787,7 +787,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
extract_cell(c, keepff); extract_cell(c, keepff);
for (auto &wire_it : module->wires_) { for (auto &wire_it : module->wires_) {
if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID(keep))) if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID::keep))
mark_port(RTLIL::SigSpec(wire_it.second)); mark_port(RTLIL::SigSpec(wire_it.second));
} }

8
passes/techmap/iopadmap.cc
View file

@ -226,7 +226,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire); cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig); cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit); cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
cell->attributes[ID(keep)] = RTLIL::Const(1); cell->attributes[ID::keep] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) { for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn); auto c = module->cell(cn);
@ -263,7 +263,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig); cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit); cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
cell->attributes[ID(keep)] = RTLIL::Const(1); cell->attributes[ID::keep] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) { for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn); auto c = module->cell(cn);
@ -390,7 +390,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
cell->attributes[ID(keep)] = RTLIL::Const(1); cell->attributes[ID::keep] = RTLIL::Const(1);
} }
} }
else else
@ -403,7 +403,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes[ID(keep)] = RTLIL::Const(1); cell->attributes[ID::keep] = RTLIL::Const(1);
} }
wire->port_id = 0; wire->port_id = 0;

4
passes/techmap/shregmap.cc
View file

@ -263,7 +263,7 @@ struct ShregmapWorker
{ {
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->port_output || wire->get_bool_attribute(ID(keep))) { if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
for (auto bit : sigmap(wire)) { for (auto bit : sigmap(wire)) {
sigbit_with_non_chain_users.insert(bit); sigbit_with_non_chain_users.insert(bit);
if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
@ -283,7 +283,7 @@ struct ShregmapWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep))) if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep))
{ {
IdString d_port = opts.ffcells.at(cell->type).first; IdString d_port = opts.ffcells.at(cell->type).first;
IdString q_port = opts.ffcells.at(cell->type).second; IdString q_port = opts.ffcells.at(cell->type).second;

2
passes/techmap/techmap.cc
View file

@ -145,7 +145,7 @@ struct TechmapWorker
record.wire = it.second; record.wire = it.second;
record.value = it.second; record.value = it.second;
result[p].push_back(record); result[p].push_back(record);
it.second->attributes[ID(keep)] = RTLIL::Const(1); it.second->attributes[ID::keep] = RTLIL::Const(1);
it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1); it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
} }
} }