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Use ID::keep more liberally too

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This commit is contained in:
Eddie Hung 2019-08-15 14:51:12 -07:00
parent 52355f5185
commit eae5a6b12c
10 changed files with 19 additions and 19 deletions
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4
passes/techmap/abc.cc
View file

@ -198,7 +198,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
if (keepff)
for (auto &c : sig_q.chunks())
if (c.wire != NULL)
c.wire->attributes[ID(keep)] = 1;
c.wire->attributes[ID::keep] = 1;
assign_map.apply(sig_d);
assign_map.apply(sig_q);
@ -787,7 +787,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
extract_cell(c, keepff);
for (auto &wire_it : module->wires_) {
if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID(keep)))
if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID::keep))
mark_port(RTLIL::SigSpec(wire_it.second));
}

8
passes/techmap/iopadmap.cc
View file

@ -226,7 +226,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
cell->attributes[ID(keep)] = RTLIL::Const(1);
cell->attributes[ID::keep] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn);
@ -263,7 +263,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
cell->attributes[ID(keep)] = RTLIL::Const(1);
cell->attributes[ID::keep] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn);
@ -390,7 +390,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
cell->attributes[ID(keep)] = RTLIL::Const(1);
cell->attributes[ID::keep] = RTLIL::Const(1);
}
}
else
@ -403,7 +403,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes[ID(keep)] = RTLIL::Const(1);
cell->attributes[ID::keep] = RTLIL::Const(1);
}
wire->port_id = 0;

4
passes/techmap/shregmap.cc
View file

@ -263,7 +263,7 @@ struct ShregmapWorker
{
for (auto wire : module->wires())
{
if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
for (auto bit : sigmap(wire)) {
sigbit_with_non_chain_users.insert(bit);
if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
@ -283,7 +283,7 @@ struct ShregmapWorker
for (auto cell : module->cells())
{
if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep)))
if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep))
{
IdString d_port = opts.ffcells.at(cell->type).first;
IdString q_port = opts.ffcells.at(cell->type).second;

2
passes/techmap/techmap.cc
View file

@ -145,7 +145,7 @@ struct TechmapWorker
record.wire = it.second;
record.value = it.second;
result[p].push_back(record);
it.second->attributes[ID(keep)] = RTLIL::Const(1);
it.second->attributes[ID::keep] = RTLIL::Const(1);
it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
}
}