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synth_intel: cyclone10 -> cyclone10lp

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This commit is contained in:
Dan Ravensloft 2019-12-10 13:31:45 +00:00
parent fcce94010f
commit eab3272cde
5 changed files with 4 additions and 4 deletions
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2
techlibs/intel/Makefile.inc
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@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
# Add the cell models and mappings for the VQM backend # Add the cell models and mappings for the VQM backend
families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))

0
techlibs/intel/cyclone10/cells_arith.v → techlibs/intel/cyclone10lp/cells_arith.v
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0
techlibs/intel/cyclone10/cells_map.v → techlibs/intel/cyclone10lp/cells_map.v
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0
techlibs/intel/cyclone10/cells_sim.v → techlibs/intel/cyclone10lp/cells_sim.v
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6
techlibs/intel/synth_intel.cc
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@ -36,10 +36,10 @@ struct SynthIntelPass : public ScriptPass {
log("\n"); log("\n");
log("This command runs synthesis for Intel FPGAs.\n"); log("This command runs synthesis for Intel FPGAs.\n");
log("\n"); log("\n");
log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); log(" -family <max10 | a10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n"); log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if no family argument specified.\n"); log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
log(" Cyclone V and Arria 10 GX devices are experimental.\n"); log(" Cyclone V and Arria 10 GX devices are experimental.\n");
log("\n"); log("\n");
log(" -top <module>\n"); log(" -top <module>\n");
@ -152,7 +152,7 @@ struct SynthIntelPass : public ScriptPass {
family_opt != "cyclonev" && family_opt != "cyclonev" &&
family_opt != "cycloneiv" && family_opt != "cycloneiv" &&
family_opt != "cycloneive" && family_opt != "cycloneive" &&
family_opt != "cyclone10") family_opt != "cyclone10lp")
log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str()); log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n"); log_header(design, "Executing SYNTH_INTEL pass.\n");