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Use read_techlib where applicable in tests

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This commit is contained in:
Miodrag Milanovic 2026-06-12 15:27:48 +02:00
parent 0dfbd13fe7
commit ea70de2165
18 changed files with 34 additions and 34 deletions
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2
tests/arch/quicklogic/qlf_k6n10f/dsp.ys
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@ -114,7 +114,7 @@ always @(posedge clk) begin
end
endmodule
EOF
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
read_techlib +/quicklogic/qlf_k6n10f/dsp_sim.v
hierarchy -top testbench
proc
async2sync

2
tests/arch/quicklogic/qlf_k6n10f/meminit.ys
View file

@ -8,7 +8,7 @@ select -assert-none t:$mem_v2 t:$mem
select -assert-count 1 t:TDP36K
select -assert-count 1 t:TDP36K a:is_split=0 %i
select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i
read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
read_techlib +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
prep
async2sync
hierarchy -top top