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fixed tests

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This commit is contained in:
Miodrag Milanovic 2023-08-23 10:54:29 +02:00
parent 75fd706487
commit ea50d96135
10 changed files with 20 additions and 21 deletions
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2
tests/arch/machxo2/add_sub.ys
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@ -1,7 +1,7 @@
read_verilog ../common/add_sub.v read_verilog ../common/add_sub.v
hierarchy -top top hierarchy -top top
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:LUT4 select -assert-count 10 t:LUT4

8
tests/arch/machxo2/adffs.ys
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@ -3,7 +3,7 @@ design -save read
hierarchy -top adff hierarchy -top adff
proc proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF
@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D
design -load read design -load read
hierarchy -top adffn hierarchy -top adffn
proc proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF
@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read design -load read
hierarchy -top dffs hierarchy -top dffs
proc proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF
@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read design -load read
hierarchy -top ndffnr hierarchy -top ndffnr
proc proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF

2
tests/arch/machxo2/counter.ys
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@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top hierarchy -top top
proc proc
flatten flatten
equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:CCU2D select -assert-count 4 t:CCU2D

6
tests/arch/machxo2/dffs.ys
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@ -3,7 +3,7 @@ design -save read
hierarchy -top dff hierarchy -top dff
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF
@ -12,8 +12,8 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:TRELLIS_FF t:LUT4 select -assert-count 1 t:TRELLIS_FF t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D

2
tests/arch/machxo2/fsm.ys
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@ -3,7 +3,7 @@ hierarchy -top fsm
proc proc
flatten flatten
equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut
miter -equiv -make_assert -flatten gold gate miter miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

2
tests/arch/machxo2/logic.ys
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@ -1,7 +1,7 @@
read_verilog ../common/logic.v read_verilog ../common/logic.v
hierarchy -top top hierarchy -top top
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4 select -assert-count 9 t:LUT4

2
tests/arch/machxo2/lutram.ys
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@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r hierarchy -top lutram_1w1r
proc proc
memory -nomap memory -nomap
equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut
memory memory
opt -full opt -full

8
tests/arch/machxo2/mux.ys
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@ -3,7 +3,7 @@ design -save read
hierarchy -top mux2 hierarchy -top mux2
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux4 hierarchy -top mux4
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux8 hierarchy -top mux8
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4 select -assert-count 5 t:LUT4
@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux16 hierarchy -top mux16
proc proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4 select -assert-max 12 t:LUT4

2
tests/arch/machxo2/shifter.ys
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@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
hierarchy -top top hierarchy -top top
proc proc
flatten flatten
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module

7
tests/arch/machxo2/tribuf.ys
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@ -2,9 +2,8 @@ read_verilog ../common/tribuf.v
hierarchy -top tristate hierarchy -top tristate
proc proc
flatten flatten
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module cd tristate # Constrain all select calls below inside the top module
select -assert-count 3 t:TRELLIS_IO select -assert-count 1 t:$_TBUF_
select -assert-count 1 t:LUT4 select -assert-none t:$_TBUF_ %% t:* %D
select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D