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fixed tests

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This commit is contained in:
Miodrag Milanovic 2023-08-23 10:54:29 +02:00
parent 75fd706487
commit ea50d96135
10 changed files with 20 additions and 21 deletions
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8
tests/arch/machxo2/mux.ys
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@ -3,7 +3,7 @@ design -save read
hierarchy -top mux2
proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4