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rtlil: Add wire deletion test

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This commit is contained in:
Martin Povišer 2024-01-22 14:42:45 +01:00
parent c035289383
commit ea3dc7c1b4
1 changed files with 8 additions and 0 deletions
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8
tests/various/bug4082.ys Normal file
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@ -0,0 +1,8 @@
read_verilog <<EOF
module top;
wire a;
wire b;
assign a = b;
endmodule
EOF
delete w:a