From 495a7805ec7e00818f3a57420140b2adcf89afb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Nov 2024 15:59:03 +0100 Subject: [PATCH 1/6] aiger2: Support `$extern:` hierarchy `$extern:...` modules inserted by `techmap -extern` are special in the regard that they have a private ID (starting with a dollar sign) but are not an internal cell. Support those modules in xaiger export. --- backends/aiger2/aiger.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 141217fe5..49d0e7fbc 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -832,12 +832,8 @@ struct XAigerAnalysis : Index { return false; Cell *driver = bit.wire->driverCell(); - if (!driver->type.isPublic()) - return false; - Module *mod = design->module(driver->type); - log_assert(mod); - if (!mod->has_attribute(ID::abc9_box_id)) + if (!mod || !mod->has_attribute(ID::abc9_box_id)) return false; int max = 1; @@ -870,7 +866,7 @@ struct XAigerAnalysis : Index { HierCursor cursor; for (auto box : top_minfo->found_blackboxes) { Module *def = design->module(box->type); - if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id))) + if (!(def && def->has_attribute(ID::abc9_box_id))) for (auto &conn : box->connections_) if (box->output(conn.first)) for (auto bit : conn.second) @@ -885,7 +881,7 @@ struct XAigerAnalysis : Index { for (auto box : top_minfo->found_blackboxes) { Module *def = design->module(box->type); - if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id))) + if (!(def && def->has_attribute(ID::abc9_box_id))) for (auto &conn : box->connections_) if (box->input(conn.first)) for (auto bit : conn.second) From 285f24d764d1231feca66235ce23e3b7d4a37601 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Nov 2024 16:01:17 +0100 Subject: [PATCH 2/6] abc_new: Support per-module script override --- passes/techmap/abc_new.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index eefe34f84..007a4e700 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -131,12 +131,26 @@ struct AbcNewPass : public ScriptPass { active_design->selection().select(mod); } + std::string script_save; + if (mod->has_attribute(ID(abc9_script))) { + script_save = active_design->scratchpad_get_string("abc9.script"); + active_design->scratchpad_set_string("abc9.script", + mod->get_string_attribute(ID(abc9_script))); + } + run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str())); run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str())); run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str())); run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig", modname.c_str(), tmpdir.c_str(), tmpdir.c_str())); + if (mod->has_attribute(ID(abc9_script))) { + if (script_save.empty()) + active_design->scratchpad_unset("abc9.script"); + else + active_design->scratchpad_set_string("abc9.script", script_save); + } + if (!help_mode) { active_design->selection().selected_modules.clear(); log_pop(); From 2a3f60bc069ad1849ee7a79b20864aeb8b5ce3b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Nov 2024 16:05:39 +0100 Subject: [PATCH 3/6] abc_new: Support `abc9_box` mode on ordinary design hierarchy Previously the `abc9_box` mode was reserved to modules with the `blackbox` or `whitebox` attribute. Allow `abc9_box` on ordinary modules when doing hierarchical synthesis. --- passes/techmap/abc9_ops.cc | 3 ++- passes/techmap/abc_new.cc | 38 +++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 378f29042..a6c86b45c 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1078,7 +1078,8 @@ void prep_box(RTLIL::Design *design) } ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int(); - ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); + bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox); + ss << " " << (has_model ? "1" : "0"); ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl; bool first = true; diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 007a4e700..2c3eef748 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -19,10 +19,29 @@ #include "kernel/register.h" #include "kernel/rtlil.h" +#include "kernel/utils.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +std::vector order_modules(Design *design, std::vector modules) +{ + std::set modules_set(modules.begin(), modules.end()); + TopoSort sort; + + for (auto m : modules) { + sort.node(m); + + for (auto cell : m->cells()) { + Module *submodule = design->module(cell->type); + if (modules_set.count(submodule)) + sort.edge(submodule, m); + } + } + log_assert(sort.sort()); + return sort.sorted; +} + struct AbcNewPass : public ScriptPass { AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)") { @@ -101,6 +120,15 @@ struct AbcNewPass : public ScriptPass { } if (check_label("prep_boxes")) { + if (!help_mode) { + for (auto mod : active_design->selected_whole_modules_warn()) { + if (mod->get_bool_attribute(ID::abc9_box)) { + mod->set_bool_attribute(ID::abc9_box, false); + mod->set_bool_attribute(ID(abc9_deferred_box), true); + } + } + } + run("box_derive"); run("abc9_ops -prep_box"); } @@ -109,7 +137,8 @@ struct AbcNewPass : public ScriptPass { std::vector selected_modules; if (!help_mode) { - selected_modules = active_design->selected_whole_modules_warn(); + selected_modules = order_modules(active_design, + active_design->selected_whole_modules_warn()); active_design->selection_stack.emplace_back(false); } else { selected_modules = {nullptr}; @@ -154,6 +183,13 @@ struct AbcNewPass : public ScriptPass { if (!help_mode) { active_design->selection().selected_modules.clear(); log_pop(); + + if (mod->get_bool_attribute(ID(abc9_deferred_box))) { + mod->set_bool_attribute(ID(abc9_deferred_box), false); + mod->set_bool_attribute(ID::abc9_box, true); + Pass::call_on_module(active_design, mod, "portarcs -draw -write"); + run("abc9_ops -prep_box"); + } } } From 559209c8560adcdbcbf8af5107e4c6b6b8fc1ea8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Nov 2024 16:05:58 +0100 Subject: [PATCH 4/6] abc_new: Fix PI confusion in whitebox model export --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 49d0e7fbc..c7ed3b81f 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1102,7 +1102,7 @@ struct XAigerWriter : AigerWriter { holes_module->ports.push_back(w->name); holes_pis.push_back(w); } - in_conn.append(holes_pis[i]); + in_conn.append(holes_pis[holes_pi_idx]); holes_pi_idx++; } holes_wb->setPort(port_id, in_conn); From 6b343c26007ec203a3943319686eb85d81f293b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Nov 2024 16:06:43 +0100 Subject: [PATCH 5/6] aiger2: Clean debug print --- frontends/aiger2/xaiger.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 3d502edf1..616bec9e7 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -203,7 +203,6 @@ struct Xaiger2Frontend : public Frontend { /* unused box_id = */ read_be32(*f); auto box_seq = read_be32(*f); - log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size()); log_assert(box_seq < boxes.size()); auto [cell, def] = boxes[box_seq]; From 0bb139dc2593c04e963387c95c7a3191098462f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 13 Nov 2024 17:51:11 +0100 Subject: [PATCH 6/6] abc_new: Fix help crash --- passes/techmap/abc_new.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 2c3eef748..5be823916 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -161,7 +161,7 @@ struct AbcNewPass : public ScriptPass { } std::string script_save; - if (mod->has_attribute(ID(abc9_script))) { + if (!help_mode && mod->has_attribute(ID(abc9_script))) { script_save = active_design->scratchpad_get_string("abc9.script"); active_design->scratchpad_set_string("abc9.script", mod->get_string_attribute(ID(abc9_script))); @@ -173,7 +173,7 @@ struct AbcNewPass : public ScriptPass { run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig", modname.c_str(), tmpdir.c_str(), tmpdir.c_str())); - if (mod->has_attribute(ID(abc9_script))) { + if (!help_mode && mod->has_attribute(ID(abc9_script))) { if (script_save.empty()) active_design->scratchpad_unset("abc9.script"); else