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Simulation model verilog fix

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This commit is contained in:
Miodrag Milanovic 2019-06-26 18:34:34 +02:00
parent 0b7d648c6a
commit ea0b6258ab
2 changed files with 1 additions and 14 deletions
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2
techlibs/xilinx/cells_sim.v
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@ -282,7 +282,7 @@ module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;