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Simulation model verilog fix

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This commit is contained in:
Miodrag Milanovic 2019-06-26 18:34:34 +02:00
parent 0b7d648c6a
commit ea0b6258ab
2 changed files with 1 additions and 14 deletions
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13
techlibs/ecp5/cells_sim.v
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@ -281,19 +281,6 @@ endmodule
// ---------------------------------------
module OB(input I, output O);
assign O = I;
endmodule
// ---------------------------------------
module BB(input I, T, output O, inout B);
assign B = T ? 1'bz : I;
assign O = B;
endmodule
// ---------------------------------------
module INV(input A, output Z);
assign Z = !A;
endmodule